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MH16S72PJB-8 Schematic ( PDF Datasheet ) - Mitsubishi

Teilenummer MH16S72PJB-8
Beschreibung 1207959552-BIT ( 16777216-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
Hersteller Mitsubishi
Logo Mitsubishi Logo 




Gesamt 30 Seiten
MH16S72PJB-8 Datasheet, Funktion
P rSepl iemci.n a r y
MITSUBISHI LSIs
MH16S72PJB-7, -8
1207959552-BIT ( 16777216-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
PRELIMINARY
Some of contents are subject to change without notice.
DESCRIPTION
The MH16S72PJB is 16777216 - word x 72-bit
Synchronous DRAM module. This consist of nine industry
standard 16M x 8 Synchronous DRAMs in TSOP.
The mounting of TSOP on a card edge dual in-line package
provides any application where high densities and large of
quantities memory are required.
This is a socket-type memory module ,suitable for easy
interchange or addition of module.
85pin 1pin
FEATURES
Type name
MH16S72PJB-7
MH16S72PJB-8
Max.
Frequency
100MHz
100MHz
CLK
Access Time
[component level]
6ns (CL = 2, 3)
6ns (CL = 3)
Utilizes industry standard 16M X 8 Synchronous DRAMs in
TSOP package , industry standard Resistered buffer in
TSSOP package and industry standard PLL in TSSOP
package
Single 3.3V +/- 0.3V supply
LVTTL Interface
Burst length 1/2/4/8/Full Page(programmable)
Burst Write / Single Write(programmable)
Auto precharge / All bank precharge controlled by A10
Auto refresh and Self refresh
4096 refresh cycles every 64ms
Discrete IC and module design conform to
PC/100 specification.
(module Spec. Rev. 1.0 and SPD 1.2A)
94pin
95pin
10pin
11pin
124pin 40pin
125pin 41pin
APPLICATION
Main memory unit for computers, Microcomputer memory.
168pin 84pin
MIT-DS-0302-0.0
MITSUBISHI
ELECTRIC
11/Jan. /1999
1






MH16S72PJB-8 Datasheet, Funktion
P rSepl iemci.n a r y
MITSUBISHI LSIs
MH16S72PJB-7, -8
1207959552-BIT ( 16777216-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
COMMAND TRUTH TABLE
COMMAND
Deselect
No Operation
MNEMONIC
CK
n-1
DESEL
NOP
H
H
CK
n
X
X
/S /RAS /CAS /WE BA
HX X X X
LH H H X
A10 A0-9
XX
XX
Row Adress Entry &
Bank Activate
ACT
H XL L H H V V V
Single Bank Precharge
Precharge All Bank
Column Address Entry
& Write
PRE
PREA
WRITE
H XL L H L
H XL L H L
H X L LH H L
VL X
VHX
VL V
Column Address Entry
& Write with Auto-
WRITEA H X L H L L V H V
Precharge
Column Address Entry
& Read
READ
H XL H L H V L V
Column Address Entry
& Read with Auto
Precharge
Auto-Refresh
Self-Refresh Entry
Self-Refresh Exit
Burst Terminate
Mode Register Set
READA
REFA
REFS
REFSX
TERM
MRS
H XL H L H V H V
H H L HL L H X X X
H LLL L H X X X
L H H LX X X X X X
L HL H H H X X X
H XL H H L X X X
H X L L L L L L V*1
H =High Level, L = Low Level, V = Valid, X = Don't Care, n = CK cycle number
NOTE:
1.A7-9 = 0, A0-6 = Mode Address
MIT-DS-0302-0.0
MITSUBISHI
ELECTRIC
11/Jan. /1999
6

6 Page









MH16S72PJB-8 pdf, datenblatt
P rSepl iemci.n a r y
MITSUBISHI LSIs
MH16S72PJB-7, -8
1207959552-BIT ( 16777216-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
POWER ON SEQUENCE
Before starting normal operation, the following power on sequence is necessary to prevent a
SDRAM from damaged or malfunctioning.
1. Apply power and start clock. Attempt to maintain CKE high, DQMB high and NOP
condition at the inputs.
2. Maintain stable power, stable cock, and NOP input conditions for a minimum of 500µs.
3. Issue precharge commands for all banks. (PRE or PREA)
4. After all banks become idle state (after tRP), issue 8 or more auto-refresh commands.
5. Issue a mode register set command to initialize the mode register.
After these sequence, the SDRAM is idle state and ready for normal operation.
MODE REGISTER
Burst Length, Burst Type and /CAS Latency can be programmed by setting the mode
register(MRS). The mode register stores these date until the next MRS command, which may
be issue when both banks are in idle state. After tRSC from a MRS command, the SDRAM is
ready for new command.
CK
/S
BA0 BA1 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
/RAS
0 0 0 0 WM 0 0 LTMODE BT
BL
/CAS
/WE
BA0,1 A11-0
V
LATENCY
MODE
CL
000
001
010
011
100
101
110
111
/CAS LATENCY
R
R
2
3
R
R
R
R
WRITE
MODE
0 BURST
1 SINGLE BIT
BURST
LENGTH
BL
000
001
010
011
100
101
110
111
BT= 0
1
2
4
8
R
R
R
FP
BT= 1
1
2
4
8
R
R
R
R
BURST
TYPE
0 SEQUENTIAL
1 INTERLEAVED
R:Reserved for Future Use
FP: Full Page
MIT-DS-0302-0.0
MITSUBISHI
ELECTRIC
11/Jan. /1999
12

12 Page





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