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MH16S72BAMD-6 Schematic ( PDF Datasheet ) - Mitsubishi

Teilenummer MH16S72BAMD-6
Beschreibung 1 /207 /959 /552-BIT ( 16 /777 /216-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
Hersteller Mitsubishi
Logo Mitsubishi Logo 




Gesamt 30 Seiten
MH16S72BAMD-6 Datasheet, Funktion
MITSUBISHI LSIs
MH16S72BAMD-6
1,207,959,552-BIT ( 16,777,216-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
PRELIMINARY
Some of contents are subject to change without notice.
DESCRIPTION
The MH16S72BAMD is 16777216 - word x 72-bit
Synchronous DRAM module. This consist of eighteen
industry standard 8M x 8 Synchronous DRAMs in TSOP.
The TSOP on a card edge dual in-line package provides any
application where high densities and large of quantities
memory are required.
This is a socket-type memory module ,suitable for easy
interchange or addition of module.
FEATURES
Type name
Max.
Frequency
Access Time from CLK
[component level]
MH16S72BAMD-6
133MHz
5.4ns
(CL = 3)
85pin
94pin
95pin
1pin
10pin
11pin
Utilizes industry standard 8M X 8 Synchronous DRAMs in TSOP
package
Single 3.3V +/- 0.3V supply
Max.Clock frequency 133MHz
Fully synchronous operation referenced to clock rising edge
4-bank operation controlled by BA0,BA1(Bank Address)
/CAS latency -2/3(programmable,at buffer mode)
LVTTL Interface
Burst length 1/2/4/8/Full Page(programmable)
Burst type- Sequential and interleave burst (programmable)
Random column access
Burst Write / Single Write(programmable)
Auto precharge / All bank precharge controlled by A10
Auto refresh and Self refresh
4096 refresh cycles every 64ms
124pin 40pin
125pin 41pin
APPLICATION
Main memory or graphic memory in computer systems
168pin 84pin
MIT-DS-0314-0.0
MITSUBISHI
ELECTRIC
10/May. /1999 1






MH16S72BAMD-6 Datasheet, Funktion
MITSUBISHI LSIs
MH16S72BAMD-6
1,207,959,552-BIT ( 16,777,216-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
COMMAND TRUTH TABLE
COMMAND
Deselect
No Operation
MNEMONIC
CKE
n-1
CKE
n
/S
/RAS /CAS /WE BA0,1 A11
A10 A0-9
DESEL
H X HX
X XX
XXX
NOP
H XLH H HX X X X
Row Adress Entry &
Bank Activate
ACT
H XLL
H HV
VVV
Single Bank Precharge
Precharge All Bank
PRE
PREA
H XLL
H XLL
H LV
H LX
XL X
X HX
Column Address Entry
& Write
WRITE
H XLH L L V
XLV
Column Address Entry
& Write with Auto-
WRITEA H X L H L L V X H V
Precharge
Column Address Entry
& Read
READ
H XLH L HV X L V
Column Address Entry
& Read with Auto
Precharge
Auto-Refresh
Self-Refresh Entry
Self-Refresh Exit
Burst Terminate
Mode Register Set
READA
REFA
REFS
REFSX
TBST
MRS
H XLH
H HLL
H L LL
L H HX
L HLH
H XLH
H XLL
L HV
L HX
L HX
X XX
H HX
H LX
L LL
X HV
XXX
XXX
XXX
XXX
XXX
L L V*1
H =High Level, L = Low Level, V = Valid, X = Don't Care, n = CK cycle number
NOTE:
1.A7-9 = 0, A0-6 = Mode Address
MIT-DS-0314-0.0
MITSUBISHI
ELECTRIC
10/May. /1999 6

6 Page









MH16S72BAMD-6 pdf, datenblatt
MITSUBISHI LSIs
MH16S72BAMD-6
1,207,959,552-BIT ( 16,777,216-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
POWER ON SEQUENCE
Before starting normal operation, the following power on sequence is necessary to prevent
a SDRAM from damaged or malfunctioning.
1. Clock will be applied at power up along with power. Attempt to maintain CKE high, DQMB
high and NOP condition at the inputs along with power.
2. Maintain stable power, stable cock, and NOP input conditions for a minimum of 200µs.
3. Issue precharge commands for all banks. (PRE or PREA)
4. After all banks become idle state (after tRP), issue 8 or more auto-refresh commands.
5. Issue a mode register set command to initialize the mode register.
After these sequence, the SDRAM is idle state and ready for normal operation.
MODE REGISTER
Burst Length, Burst Type and /CAS Latency can be programmed by setting the mode
register(MRS). The mode register stores these date until the next MRS command, which
may be issue when both banks are in idle state. After tRSC from a MRS command, the
SDRAM is ready for new command.
CK
BA0 BA1 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
0 0 0 0 WM 0 0 LTMODE BT
BL
/S
/RAS
/CAS
/WE
BA0,1 A11-0
V
LATENCY
MODE
CL
000
001
010
011
100
101
110
111
/CAS LATENCY
R
R
2
3
R
R
R
R
BURST
LENGTH
BL
000
001
010
011
100
101
110
111
BT= 0
1
2
4
8
R
R
R
FP
BT= 1
1
2
4
8
R
R
R
R
BURST
TYPE
0 SEQUENTIAL
1 INTERLEAVED
WRITE
MODE
0 BURST
1 SINGLE BIT
R:Reserved for Future Use
FP: Full Page
MIT-DS-0314-0.0
MITSUBISHI
ELECTRIC
10/May. /1999 12

12 Page





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