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MH16S64BAMD-8 Schematic ( PDF Datasheet ) - Mitsubishi

Teilenummer MH16S64BAMD-8
Beschreibung 1073741824-BIT (16777216 - WORD BY 64-BIT)SynchronousDRAM
Hersteller Mitsubishi
Logo Mitsubishi Logo 




Gesamt 30 Seiten
MH16S64BAMD-8 Datasheet, Funktion
Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH16S64BAMD -7,-8,-10
1073741824-BIT (16777216 - WORD BY 64-BIT)SynchronousDRAM
DESCRIPTION
The MH16S64BAMD is 16777216 word X 64 bit
Synchronous DRAM module. This consists of sixteen
industry standard 8Mx8 Synchronous DRAMs in
TSOP and one industory standard EEPROM in
TSSOP.
The mounting of TSOP on a card edge Dual Inline
package provides any application where high
densities and large quantities of memory are
required.
This is a socket type - memory modules, suitable for
easy interchange or addition of modules.
FEATURES
Frequency
CLK Access Time
(Component SDRAM)
-7 100MHz 6.0ns(CL=3)
-8 100MHz 6.0ns(CL=3)
-10 100MHz
8.0ns(CL=3)
Utilizes industry standard 8M x 8 Synchronous DRAMs
TSOP and industry standard EEPROM in TSSOP
168-pin (84-pin dual in-line package)
single 3.3V±0.3V power supply
Clock frequency 100MHz
Fully synchronous operation referenced to clock rising
edge
4 bank operation controlled by BA0,1(Bank Address)
/CAS latency- 2/3(programmable)
Burst length- 1/2/4/8/Full Page(programmable)
Burst type- sequential / interleave(programmable)
Column access - random
Auto precharge / All bank precharge controlled by A10
Auto refresh and Self refresh
4096 refresh cycle /64ms
LVTTL Interface
Discrete IC and module design conform to
PC100 specification.
(module Spec. Rev. 1.0 and
SPD 1.2A(-7,-8), SPD 1.0(-10))
APPLICATION
PC main memory
85pin 1pin
94pin
95pin
10pin
11pin
124pin 40pin
125pin 41pin
168pin 84pin
MIT-DS-0212-0.4
MITSUBISHI
ELECTRIC
( 1 / 55 )
29. Oct.1998






MH16S64BAMD-8 Datasheet, Funktion
Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH16S64BAMD -7,-8,-10
1073741824-BIT (16777216 - WORD BY 64-BIT)SynchronousDRAM
COMMAND TRUTH TABLE
COMMAND
Deselect
No Operation
MNEMONIC
CKE
n-1
CKE
n
/S
/RAS /CAS /WE BA0,1 A11
A10 A0-9
DESEL
NOP
H XHX X X X X X X
H XL H H H X X X X
Row Adress Entry &
Bank Activate
ACT
H XL L H H V V V V
Single Bank Precharge
Precharge All Bank
Column Address Entry
& Write
PRE
PREA
WRITE
H XL L
H XL L
HL
HL
H XL H L L
VXL X
XXHX
VXL V
Column Address Entry
& Write with Auto-
WRITEA H X L H L L V X H V
Precharge
Column Address Entry
& Read
READ
H XL H L H V X L V
Column Address Entry
& Read with Auto
Precharge
Auto-Refresh
Self-Refresh Entry
Self-Refresh Exit
Burst Terminate
Mode Register Set
READA
REFA
REFS
REFSX
TERM
MRS
H XL H L H V X H V
H HL L L H X X X X
H LLL L H X X X X
L HHX X X X X X X
L HL H H H X X X X
H XL H H L X X X X
H X L L L L L L L V*1
H =High Level, L = Low Level, V = Valid, X = Don't Care, n = CK cycle number
NOTE:
1.A7-9 = 0, A0-6 = Mode Address
MIT-DS-0212-0.4
MITSUBISHI
ELECTRIC
( 6 / 55 )
29. Oct.1998

6 Page









MH16S64BAMD-8 pdf, datenblatt
Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH16S64BAMD -7,-8,-10
1073741824-BIT (16777216 - WORD BY 64-BIT)SynchronousDRAM
SIMPLIFIED STATE DIAGRAM
SELF
REFRESH
REFS
REFSX
MODE
REGISTER
SET
MRS
IDLE
REFA
AUTO
REFRESH
CKEL
CLK
SUSPEND
CKEH
ACT
CKEL
POWER
DOWN
CKEH
TBST(for Full Page)
ROW
ACTIVE
TBST(for Full Page)
WRITE
READ
CKEL
WRITE
SUSPEND
CKEH
WRITE
WRITEA
READA
READ
WRITE
READ
CKEL
CKEH
READ
SUSPEND
WRITEA
CKEL
WRITEA
SUSPEND
CKEH
WRITEA
WRITEA
READA
PRE
PRE
PRE
READA
READA
CKEL
CKEH
READA
SUSPEND
POWER
APPLIED
POWER
ON
PRE
PRE
CHARGE
Automatic Sequence
Command Sequence
MIT-DS-0212-0.4
MITSUBISHI
ELECTRIC
( 12 / 55 )
29. Oct.1998

12 Page





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