Datenblatt-pdf.com


MH16M40AJD-6 Schematic ( PDF Datasheet ) - Mitsubishi

Teilenummer MH16M40AJD-6
Beschreibung FAST PAGE MODE ( 16 /777 /216-WORD BY 40-BIT ) DYNAMIC RAM
Hersteller Mitsubishi
Logo Mitsubishi Logo 




Gesamt 17 Seiten
MH16M40AJD-6 Datasheet, Funktion
Preliminary Spec.
MITSUBISHI LSIs
Some of contents are subject to change without notice.
MH16M40AJD -6
Proto-2
FAST PAGE MODE ( 16,777,216-WORD BY 40-BIT ) DYNAMIC RAM
DESCRIPTION
The MH16M40AJD is a 16M word by 40-bit dynamic
RAM module and consists of 10 industry standard
16M X 4 dynamic RAMs in a TSOP package.
The ICs are mounted on both sides of two small PC
boards (Ceracom) with the flash gold plating and form
a convenient 69-pin WDIP package.
FEATURES
Type name
MH16M40AJD-6
RAS
CAS Address OE Cycle Power
access access access access
dissipa-
time
time time
time
time
tion
(max.ns) (max.ns) (max.ns) (max.ns) (min.ns) (typ.mW)
60 15 30 15 110 2500
Utilizes industry standard 16M X 4 DRAMs in TSOP package
Low stand-by power dissipation
13mW (Max) ............................ CMOS lnput level
Low operating power dissipation
MH16M40AJD - 6 ........................ 3242 mW (Max)
Fast-page mode , Read-modify-write,RAS-only refresh
CAS before RAS refresh, Hidden refresh capabilities
Early-write mode and OE to control output buffer impedance
All inputs, output TTL compatible and low capacitance
4096 refresh cycles every 64ms (A0 - A12) (CbR only)
Includes (0.22uF x 12) decoupling capacitors
5.0V ± 5% Vcc
3.3V Vdd by onboard mounted regulators
TTL input converted to LVTTL by onboard mounted level
shifters.
APPLICATION
Main memory unit for computers, Microcomputer memory,
Refresh memory for CRT
PIN DESCRIPTION
Pin Name Function
A0-A12
Address Inputs
DQ1-DQ40 Data Inputs / Outputs
RAS 0
Row Address Strobe Input
CAS 0
Column Address Strobe Input
W 0 Write Control Input
OE 0
Output Enable Input
Vcc Power Supply (+5V)
Vss Ground (0V)
PIN CONFIGURATION ( TOP VIEW )
DQ1 1
DQ2 2
DQ3 3
DQ4 4
DQ5 5
DQ6 6
Vss 7
DQ7 8
DQ8 9
DQ9 10
DQ10 11
DQ11 12
DQ12 13
DQ13 14
Vcc 15
DQ14 16
/CAS0 17
/RAS0 18
DQ15 19
DQ16 20
DQ17 21
/W0 22
NC 23
DQ18 24
DQ19 25
Vss 26
DQ20 27
A0 28
A1 29
A2 30
A3 31
A4 32
A5 33
A6 34
69 Key Pin
68 Vss
67 DQ40
66 DQ39
65 DQ38
64 DQ37
63 DQ36
62 Vcc
61 DQ35
60 DQ34
59 DQ33
58 DQ32
57 DQ31
56 DQ30
55 DQ29
54 Vss
53 DQ28
52 NC
51 NC
50 DQ27
49 DQ26
48 DQ25
47 /OE0
46 NC
45 DQ24
44 DQ23
43 Vcc
42 DQ22
41 DQ21
40 A12
39 A11
38 A10
37 A9
36 A8
35 A7
MIT - DS - 0069 -1.1
MITSUBISHI
ELECTRIC
(1 / 17 )
31/ Jan./1997






MH16M40AJD-6 Datasheet, Funktion
Preliminary Spec.
MITSUBISHI LSIs
Some of contents are subject to change without notice.
MH16M40AJD -6
Proto-2
FAST PAGE MODE ( 16,777,216-WORD BY 40-BIT ) DYNAMIC RAM
Read-Write and Read-Modify-Write Cycles
Symbol
Parameter
tRWC
tRAS
tCAS
tCSH
tRSH
tRCS
tCWD
tRWD
tAWD
tCWL
tRWL
tWP
tDS
tDH
tOEH
Read write/read modify write cycle time (Note21)
RAS low pulse width
CAS low pulse width
CAS hold time after RAS low
RAS hold time after CAS low
Read setup time before CAS low
Delay time, CAS low to W low
(Note22)
Delay time, RAS low to W low
(Note22)
Delay time, address to W low
(Note22)
CAS hold time after W low
RAS hold time after W low
Write pulse width
Data setup time before W low
ÅÜ
Data hold time aÅfteÖr W low
OE hold time after W low
ÅÜ
ÅÖ
Limits
-6
Min Max
150
95 10000
50 10000
95
50
0
30
75
45
15
15
10
0
10
15
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Note 21: tRWC is specified as tRWC(min)=tRAC(max)+tODD(min)+tRWL(min)+tRP(min)+4tT.
22: tWCS, tCWD,tRWD and tAWD and,tCPWD are specified as reference points only. If tWCS tWCS(min) the cycle is an early write cycle and the
DQ pins will remain high impedance throughout the entire cycle. If tCWD tCWD(min), tRWD tRWD (min), tAWD tAWD(min) and tCPWD tCPWD(min)
(for fast page mode cycle only), the cycle is a read-modify-write cycle and the DQ will contain the data read from the selected address.
If neither of the above condition (delayed write) of the DQ (at access time and until CAS or OE goes back to VIH ) is indeterminate.
Fast-Page Mode Cycle (Read, Early Write, Read -Write, Read-Modify-Write Cycle) (Note 23)
Symbol
Parameter
tPC
tPRWC
tRAS
tCP
tCPRH
tCPWD
Fast page mode read/write cycle time
Fast page mode read write/read modify write cycle time
RAS iow pulse width for read write cycle (Note24)
CAS high pulse width
(Note25)
RAS hold time after CAS precharge
Delay time, CAS precharge to W iow
(Note22)
Limits
-6
Min Max
40
75
100 102400
10 15
35
35
Unit
ns
ns
ns
ns
ns
ns
Note 23: All previously specified timing requirements and switching characteristics are applicable to their respective fast page mode cycle.
24: tRAS(min) is specified as two cycles of CAS input are performed.
25: tCP(max) is specified as a reference point only. If tCP tCP(max),access time is controlled exclusively by tCAC.
CAS before RAS Refresh Cycle (Note 26)
Symbol
Parameter
tCSR CAS setup time before RAS low
tCHR CAS hold time after RAS low
tRSR Read setup time before RAS low
tRHR Read hold time after RAS low
Limits
-6
Min Max
10
10
10
10
Unit
ns
ns
ns
ns
Note 26: Eight or more CAS before RAS cycles instead of eight RAS cycles are necessary for proper operation of CAS before RAS refresh
mode.
MIT - DS - 0069 -1.1
MITSUBISHI
ELECTRIC
(6 / 17 )
31/ Jan./1997

6 Page









MH16M40AJD-6 pdf, datenblatt
Preliminary Spec.
MITSUBISHI LSIs
Some of contents are subject to change without notice.
MH16M40AJD -6
Proto-2
FAST PAGE MODE ( 16,777,216-WORD BY 40-BIT ) DYNAMIC RAM
Hidden Refresh Cycle (Read) (Note 28)
RAS
VIH
VIL
CAS
VIH
VIL
A0 - A12
VIH
VIL
VIH
W
VIL
tRC
tRAS
tCRP
tRCD
tRSH
tASR
tRAD
tRAH tASC
tCAH
ROW
ADDRESS
tRCS
COLUMN
ADDRESS
tRAL
tDZC
DQ VIH
(INPUTS)
VIL
DQ VOH
(OUTPUTS)
VOL
VIL
W
VIH
tCAC
tAA
tCLZ
Hi-Z
tRAC
tDZO
tOEA
tORH
tRP
tRRH
tRC
tRAS
tRP
tCHR
tASR
ROW
ADDRESS
tCDD
Hi-Z
tOFF
DATA VALID
Hi-Z
tOEZ
tODD
Note 28: Early write, delayed write, read write or read modify write cycle is applicable instead of read cycle.
Timing requirements and output state are the same as that of each cycle shown above.
MIT - DS - 0069 -1.1
MITSUBISHI
ELECTRIC
(12 / 17 )
31/ Jan./1997

12 Page





SeitenGesamt 17 Seiten
PDF Download[ MH16M40AJD-6 Schematic.PDF ]

Link teilen




Besondere Datenblatt

TeilenummerBeschreibungHersteller
MH16M40AJD-6FAST PAGE MODE ( 16 /777 /216-WORD BY 40-BIT ) DYNAMIC RAMMitsubishi
Mitsubishi

TeilenummerBeschreibungHersteller
CD40175BC

Hex D-Type Flip-Flop / Quad D-Type Flip-Flop.

Fairchild Semiconductor
Fairchild Semiconductor
KTD1146

EPITAXIAL PLANAR NPN TRANSISTOR.

KEC
KEC


www.Datenblatt-PDF.com       |      2020       |      Kontakt     |      Suche