|
|
PDF PHD24N03 Data sheet ( Hoja de datos )
| Número de pieza | PHD24N03 | |
| Descripción | TrenchMOS transistor Logic level FET | |
| Fabricantes | NXP Semiconductors | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de PHD24N03 (archivo pdf) en la parte inferior de esta página. Total 8 Páginas | ||
|
No Preview Available !
Philips Semiconductors
TrenchMOS transistor
Logic level FET
Preliminary specification
PHD24N03LT
FEATURES
• ’Trench’ technology
• Very low on-state resistance
• Fast switching
• Stable off-state characteristics
• High thermal cycling performance
• Low thermal resistance
SYMBOL
g
d
s
QUICK REFERENCE DATA
VDSS = 30 V
ID = 24 A
RDS(ON) ≤ 56 mΩ (VGS = 5 V)
RDS(ON) ≤ 50 mΩ (VGS = 10 V)
GENERAL DESCRIPTION
N-channel enhancement mode,
logic level, field-effect power
transistor in a plastic envelope
using ’trench’ technology. The
device has very low on-state
resistance. It is intended for use in
dc to dc converters and general
purpose switching applications.
The PHD24N03LT is supplied in the
SOT428 (DPAK) surface mounting
package.
PINNING
PIN
DESCRIPTION
1 gate
2 drain 1
3 source
tab drain
SOT428 (DPAK)
tab
2
13
LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134)
SYMBOL PARAMETER
CONDITIONS
VDSS
VDGR
VGS
ID
IDM
PD
Tj, Tstg
Drain-source voltage
Drain-gate voltage
Gate-source voltage
Continuous drain current
Pulsed drain current
Total power dissipation
Operating junction and
storage temperature
Tj = 25 ˚C to 175˚C
Tj = 25 ˚C to 175˚C; RGS = 20 kΩ
Tmb = 25 ˚C
Tmb = 100 ˚C
Tmb = 25 ˚C
Tmb = 25 ˚C
MIN.
-
-
-
-
-
-
-
- 55
MAX.
30
30
± 13
24
20
96
60
175
UNIT
V
V
V
A
A
A
W
˚C
THERMAL RESISTANCES
SYMBOL PARAMETER
Rth j-mb
Rth j-a
Thermal resistance junction
to mounting base
Thermal resistance junction
to ambient
CONDITIONS
pcb mounted, minimum footprint
TYP.
-
50
MAX.
2.5
-
UNIT
K/W
K/W
1 it is not possible to make connection to pin 2 of the SOT428 package.
December 1999
1
Rev 1.100
1 page  
Philips Semiconductors
TrenchMOS transistor
Logic level FET
VGS, Gate-Source voltage (Volts)
15
VDD = 15 V
ID = 24 A
Tj = 25 C
10
PHP24N03LT
5
0
0 5 10 15 20 25
Qg, Gate charge (nC)
Fig.13. Typical turn-on gate-charge characteristics.
VGS = f(QG); parameter VDS
Preliminary specification
PHD24N03LT
Source-Drain diode current, IF(A)
20
VGS = 0 V
15
PHP24N03LT
10
175 C
Tj = 25 C
5
0
0 0.2 0.4 0.6 0.8 1 1.2 1.4
Source-Drain voltage, VSDS (V)
Fig.14. Typical reverse diode current.
IF = f(VSDS); parameter Tj
December 1999
5
Rev 1.100
5 Page | ||
| Páginas | Total 8 Páginas | |
| PDF Descargar | [ Datasheet PHD24N03.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| PHD24N03 | TrenchMOS transistor Logic level FET | NXP Semiconductors |
| PHD24N03LT | TrenchMOS transistor Logic level FET | NXP Semiconductors |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |