Datenblatt-pdf.com


M95256-WDL3T Schematic ( PDF Datasheet ) - ST Microelectronics

Teilenummer M95256-WDL3T
Beschreibung 256/128 Kbit Serial SPI Bus EEPROM With High Speed Clock
Hersteller ST Microelectronics
Logo ST Microelectronics Logo 




Gesamt 21 Seiten
M95256-WDL3T Datasheet, Funktion
M95256
M95128
256/128 Kbit Serial SPI Bus EEPROM
With High Speed Clock
PRELIMINARY DATA
s SPI Bus Compatible Serial Interface
s Supports Positive Clock SPI Modes
s 5 MHz Clock Rate (maximum)
s Single Supply Voltage:
– 4.5V to 5.5V for M95xxx
– 2.7V to 3.6V for M95xxx-V
– 2.5V to 5.5V for M95xxx-W
– 1.8V to 3.6V for M95xxx-R
s Status Register
s Hardware and Software Protection of the Status
Register
s BYTE and PAGE WRITE (up to 64 Bytes)
s Self-Timed Programming Cycle
s Resizeable Read-Only EEPROM Area
s Enhanced ESD Protection
s 100,000 Erase/Write Cycles (minimum)
s 40 Year Data Retention (minimum)
DESCRIPTION
These SPI-compatible electrically erasable
programmable memory (EEPROM) devices are
organized as 32K x 8 bits (M95256) and 16K x 8
bits (M95128), and operate down to 2.7 V (for the
8
1
PSDIP8 (BN)
0.25 mm frame
8
1
SO8 (MN)
150 mil width
Figure 1. Logic Diagram
VCC
14
1
TSSOP14 (DL)
169 mil width
8
1
SO8 (MW)
200 mil width
Table 1. Signal Names
C Serial Clock
D Serial Data Input
Q Serial Data Output
S Chip Select
W Write Protect
HOLD
Hold
VCC Supply Voltage
VSS Ground
D
C
S
W
HOLD
M95xxx
VSS
Q
AI01789C
March 2000
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
1/21






M95256-WDL3T Datasheet, Funktion
M95256, M95128
Table 4. Instruction Set
Instruc
tion
Description
Instruction
Format
WREN Set Write Enable Latch
0000 0110
WRDI Reset Write Enable Latch
0000 0100
RDSR Read Status Register
0000 0101
WRSR Write Status Register
0000 0001
READ Read Data from Memory Array 0000 0011
WRITE Write Data to Memory Array 0000 0010
Table 5. Status Register Format
b7 b0
SRWD X X X BP1 BP0 WEL WIP
Note: 1. SRWD, BP0 and BP1 are Read and write bits.
2. WEL and WIP are Read only bits.
As soon as the WREN or WRDI instruction is
received, the memory device first executes the
instruction, then enters a wait mode until the
device is deselected.
Read Status Register (RDSR)
The RDSR instruction allows the status register to
be read, and can be sent at any time, even during
a Write operation. Indeed, when a Write is in
progress, it is recommended that the value of the
Write-In-Progress (WIP) bit be checked. The value
in the WIP bit (whose position in the status register
is shown in Table 5) can be continuously polled,
before sending a new WRITE instruction, using
the timing shown in Figure 7. The Write-In-
Process (WIP) bit is read-only, and indicates
whether the memory is busy with a Write
operation. A ’1’ indicates that a write is in progress,
and a ’0’ that no write is in progress.
The Write Enable Latch (WEL) bit indicates the
status of the write enable latch. It, too, is read-only.
Its value can only be changed by one of the events
listed in the previous paragraph, or as a result of
executing WREN or WRDI instruction. It cannot be
changed using a WRSR instruction. A ’1’ indicates
that the latch is set (the forthcoming Write
instruction will be executed), and a ’0’ that it is
reset (and any forthcoming Write instructions will
be ignored).
The Block Protect (BP0 and BP1) bits indicate the
amount of the memory that is to be write-
protected. These two bits are non-volatile. They
are set using a WRSR instruction.
During a Write operation (whether it be to the
memory area or to the status register), all bits of
the status register remain valid, and can be read
using the RDSR instruction. However, during a
Write operation, the values of the non-volatile bits
(SRWD, BP0, BP1) become frozen at a constant
value. The updated value of these bits becomes
available when a new RDSR instruction is
executed, after completion of the write cycle. On
the other hand, the two read-only bits (WEL, WIP)
are dynamically updated during internal write
cycles. Using this facility, it is possible to poll the
WIP bit to detect the end of the internal write cycle.
Write Status Register (WRSR)
The format of the WRSR instruction is shown in
Figure 8. After the instruction and the eight bits of
the status register have been latched-in, the
internal Write cycle is triggered by the rising edge
of the S line. This must occur before the rising
edge of the 17th clock pulse (as indicated in Figure
14), otherwise the internal write sequence is not
performed.
The WRSR instruction is used for the following:
s to select the size of memory area that is to be
write-protected
s to select between SPM (Software Protected
Mode) and HPM (Hardware Protected Mode).
Figure 7. RDSR: Read Status Register Sequence
S
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
C
INSTRUCTION
D
STATUS REG. OUT
STATUS REG. OUT
HIGH IMPEDANCE
Q 76543210765432107
MSB
MSB
MSB
AI02031
6/21

6 Page









M95256-WDL3T pdf, datenblatt
M95256, M95128
Table 12A. AC Characteristics
M95256 / M95128
Symbol Alt.
Parameter
VCC=4.5 to 5.5 V
TA=0 to 70°C or
-40 to 85°C
VCC=4.5 to 5.5 V
TA=-40 to 125°C
Unit
Min Max Min Max
fC fSCK Clock Frequency
D.C. 5 D.C. 2 MHz
tSLCH
tCSS1 S Active Setup Time
90 200 ns
tSHCH
tCSS2 S Not Active Setup Time
90 200 ns
tSHSL
tCS S Deselect Time
100 200 ns
tCHSH
tCSH S Active Hold Time
90 200 ns
tCHSL
S Not Active Hold Time
90 200 ns
tCH 1
tCLH Clock High Time
90 200 ns
tCL 1
tCLL Clock Low Time
90 200 ns
tCLCH 2
tRC Clock Rise Time
1 1 µs
tCHCL 2
tFC Clock Fall Time
1 1 µs
tDVCH
tDSU Data In Setup Time
20 40 ns
tCHDX
tDH Data In Hold Time
30 50 ns
tDLDH 2
tRI Data In Rise Time
1 1 µs
tDHDL 2
tFI Data In Fall Time
1 1 µs
tHHCH
Clock Low Hold Time after HOLD not Active
70
140 ns
tHLCH
Clock Low Hold Time after HOLD Active
40
90 ns
tCHHL
Clock High Set-up Time before HOLD Active
60
120 ns
tCHHH
Clock High Set-up Time before HOLD not Active 60
120 ns
tSHQZ 2
tDIS Output Disable Time
100 250 ns
tCLQV
tV Clock Low to Output Valid
60 150 ns
tCLQX
tHO Output Hold Time
0 0 ns
tQLQH 2
tRO Output Rise Time
50 100 ns
tQHQL 2
tFO Output Fall Time
50 100 ns
tHHQX 2
tLZ HOLD High to Output Low-Z
50 100 ns
tHLQZ 2
tHZ HOLD Low to Output High-Z
100 250 ns
tW tWC Write Time
Note: 1. tCH + tCL 1 / fC.
2. Value guaranteed by characterization, not 100% tested in production.
10 10 ms
12/21

12 Page





SeitenGesamt 21 Seiten
PDF Download[ M95256-WDL3T Schematic.PDF ]

Link teilen




Besondere Datenblatt

TeilenummerBeschreibungHersteller
M95256-WDL3T256/128 Kbit Serial SPI Bus EEPROM With High Speed ClockST Microelectronics
ST Microelectronics

TeilenummerBeschreibungHersteller
CD40175BC

Hex D-Type Flip-Flop / Quad D-Type Flip-Flop.

Fairchild Semiconductor
Fairchild Semiconductor
KTD1146

EPITAXIAL PLANAR NPN TRANSISTOR.

KEC
KEC


www.Datenblatt-PDF.com       |      2020       |      Kontakt     |      Suche