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M616Z08-20MH3TR Schematic ( PDF Datasheet ) - ST Microelectronics

Teilenummer M616Z08-20MH3TR
Beschreibung 128 Kbit 8 Kbit x 16 SRAM WITH OUTPUT ENABLE
Hersteller ST Microelectronics
Logo ST Microelectronics Logo 




Gesamt 14 Seiten
M616Z08-20MH3TR Datasheet, Funktion
M616Z08
128 Kbit (8 Kbit x 16) SRAM WITH OUTPUT ENABLE
FEATURES SUMMARY
s OPERATION VOLTAGE: 2.34V to 3.6V
s 8 Kbit x 16 SRAM
s EQUAL CYCLE and ACCESS TIMES: AS
FAST AS 20ns
s TRI-STATE COMMON I/O
s TWO WRITE ENABLE PINS ALLOW WRITING
TO UPPER AND LOWER BYTES
Figure 1. 44-pin, Hatless SOIC Package
44
1
SO44 (MH)
Figure 2. Logic Diagram
VCC
13
A0-A12
16
DQ0-DQ15
WE0
WE1
CE
OE
M616Z08
TO
VSS
AI04213
Table 1. Signal Names
A0-A12
Address Inputs
DQ0-DQ15 Data Input/Output
CE Chip Enable
OE Output Enable
WE0
WRITE Enable DQ 0-7
WE1
WRITE Enable DQ 8-15
VCC Supply Voltage
VSS Ground
TO Time-Out Pin
Note: TO Pin should be connected to VCC.
July 2002
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M616Z08-20MH3TR Datasheet, Funktion
M616Z08
Table 5. DC Characteristics
Sym
Parameter
Test Condition(1)
Min Typ Max Unit
ILI Input Leakage Current
0V VIN VCC
TO Pin(2)
All other inputs
65 125 µA
±1 µA
ILO Output Leakage Current
0V VOUT VCC
±1 µA
ICC1(3) Supply Current
VCC = 3.6V
75 mA
ICC3(4)
Supply Current (Standby)
CMOS
VCC = 3.6V,
CE VCC – 0.2V, f = 0
1 mA
VIL Input Low Voltage
–0.3
0.3VCC
V
VIH Input High Voltage
0.7VCC
VCC + 0.3 V
VOL Output Low Voltage
IOL = 1mA
0.2 V
VOH Output High Voltage
IOH = –1mA
2.34 to 3.0V
3.0 to 3.6V
VCC–0.2V
VCC–0.3V
V
Note: 1. Valid for Ambient Operating Temperature: TA = –40 to 125°C; VCC = 3.0 to 3.6V or 2.34 to 3.0V (except where noted).
2. Input leakage on TO Pin due to internal pull-down to VSS.
3. Average AC current, Outputs open, cycling at tAVAV minimum.
4. All other Inputs at VIL 0.2V or VIH VCC –0.2V.
OPERATION
READ Mode
The M616Z08 is in the READ Mode whenever
WRITE Enable (WE0 or WE1) is High with Output
Enable (OE) Low, and Chip Enable (CE) is assert-
ed. This provides access to data from sixteen of
the 131,072 locations in the static memory array,
specified by the 13 address inputs. Valid data will
be available at the sixteen output pins within tAVQV
after the last stable address, providing OE is Low
and CE is Low. If Chip Enable or Output Enable
access times are not met, data access will be
measured from the limiting parameter (tELQV or
tGLQV) rather than the address. Data out may be
indeterminate at tELQX and tGLQX, but data lines
will always be valid at tAVQV.
Figure 5. Address Controlled, READ Mode AC Waveforms
A0-A12
tAVAV
VALID
tAVQV
tAXQX
DQ0-DQ15
Note: CE = Low, OE = Low, WE(0,1) = High.
DATA VALID
AI04210
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6 Page









M616Z08-20MH3TR pdf, datenblatt
M616Z08
PACKAGE MECHANICAL INFORMATION
Figure 9. SO44 – 44-Lead, Plastic, Hatless, Small Package Outline
Be
D
N
A2
CP
A
C
EH
1
SOH-C
Note: Drawing is not to scale.
A1 α L
Table 11. SO44 – 44-lead, Plastic, Hatless, Small Package Mechanical Data
Symb
Min
mm
Typ
Max
inches
Min Typ
A 3.05
A1
0.05 0.36
0.002
A2
2.34 2.69
0.092
B
0.36 0.46
0.014
C
0.15 0.32
0.006
D
17.71
18.49
0.697
E
8.23 8.89
0.324
e 0.81 –
0.032
H
11.51
12.70
0.453
L
0.41 1.27
0.016
a
0° 8°
N 44
44
CP 0.10
Max
0.120
0.014
0.106
0.018
0.012
0.728
0.350
0.500
0.050
0.004
12/14

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