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PDF MC14501BD Data sheet ( Hoja de datos )
| Número de pieza | MC14501BD | |
| Descripción | Dual 4-Input NAND Gate / 2-Input NOR/OR Gate / 8-Input AND/NAND Gate | |
| Fabricantes | Motorola Semiconductors | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de MC14501BD (archivo pdf) en la parte inferior de esta página. Total 6 Páginas | ||
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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Triple Gate
Dual 4–Input “NAND” Gate
2–Input “NOR/OR” Gate
8–Input “AND/NAND” Gate
The MC14501UB is constructed with MOS P–channel and N–channel
enhancement mode devices in a single monolithic structure. These
complementary MOS logic gates find primary use where low power
dissipation and/or high noise immunity is desired. Additional characteristics
can be found on the Family Data Sheet.
• Diode Protection on All Inputs
• Supply Voltage Range = 3.0 Vdc to 18 Vdc
• Logic Swing Independent of Fanout
• Capable of Driving Two Low–Power TTL Loads or One Low–Power
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎSchottky TTL Load Over the Rated Temperature Range
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎMAXIMUM RATINGS* (Voltages Referenced to VSS)
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎSymbol
Parameter
Value
Unit
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎVDD DC Supply Voltage
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎVin, Vout Input or Output Voltage (DC or Transient)
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎIin, Iout Input or Output Current (DC or Transient),
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎper Pin
– 0.5 to + 18.0
– 0.5 to VDD + 0.5
± 10
V
V
mA
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎPD Power Dissipation, per Package†
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎTstg Storage Temperature
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎTL Lead Temperature(8–SecondSoldering)
500
– 65 to + 150
260
mW
_C
_C
* Maximum Ratings are those values beyond which damage to the device may occur.
†Temperature Derating:
Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C
Ceramic “L” Packages: – 12 mW/_C From 100_C To 125_C
CIRCUIT SCHEMATIC
VDD 16
VDD
11
13 (10) 12
(6) 1 14
(7) 2
(9) 3 VSS 15
(5) 4
VSS 8
VSS
Numbers in parenthesis are for second 4–input gate.
MC14501UB
L SUFFIX
CERAMIC
CASE 620
P SUFFIX
PLASTIC
CASE 648
D SUFFIX
SOIC
CASE 751B
ORDERING INFORMATION
MC14XXXBCP
MC14XXXBCL
MC14XXXBD
Plastic
Ceramic
SOIC
TA = – 55° to 125°C for all packages.
LOGIC DIAGRAM
(POSITIVE LOGIC)
1
2
3
4
11
12
5
6
7
9 VDD = PIN 16
VSS = PIN 8
13
14 AND
15 NAND
10
Use Dotted Connection Externally to
Obtain 8–Input AND/NAND
NOTE: Pin 14 must not be used as an input
NOTE: to the inverter.
REV 3
1/94
©MMOotoTrOolaR, IOncL. A199C5MOS LOGIC DATA
MC14501UB
1
1 page  
OUTLINE DIMENSIONS
L SUFFIX
CERAMIC DIP PACKAGE
CASE 620–10
ISSUE V
–A–
16 9
–B–
18
CL
–T–
SEATING
PLANE
F
NK
E
G
D 16 PL
0.25 (0.010) M T A S
M
J 16 PL
0.25 (0.010) M T B S
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEL.
4. DIMENSION F MAY NARROW TO 0.76 (0.030)
WHERE THE LEAD ENTERS THE CERAMIC
BODY.
INCHES
MILLIMETERS
DIM MIN MAX MIN MAX
A 0.750 0.785 19.05 19.93
B 0.240 0.295 6.10 7.49
C ––– 0.200 ––– 5.08
D 0.015 0.020 0.39 0.50
E 0.050 BSC
1.27 BSC
F 0.055 0.065 1.40 1.65
G 0.100 BSC
2.54 BSC
H 0.008 0.015 0.21 0.38
K 0.125 0.170 3.18 4.31
L 0.300 BSC
7.62 BSC
M 0_ 15_ 0_ 15_
N 0.020 0.040 0.51 1.01
–A–
16
1
H
G
P SUFFIX
PLASTIC DIP PACKAGE
CASE 648–08
ISSUE R
9
B
8
FC
S
L
–T–
SEATING
PLANE
KJ
D 16 PL
0.25 (0.010) M T A M
M
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.
5. ROUNDED CORNERS OPTIONAL.
INCHES
MILLIMETERS
DIM MIN MAX MIN MAX
A 0.740 0.770 18.80 19.55
B 0.250 0.270 6.35 6.85
C 0.145 0.175 3.69 4.44
D 0.015 0.021 0.39 0.53
F 0.040 0.70 1.02 1.77
G 0.100 BSC
2.54 BSC
H 0.050 BSC
1.27 BSC
J 0.008 0.015 0.21 0.38
K 0.110 0.130 2.80 3.30
L 0.295 0.305 7.50 7.74
M 0_ 10_ 0_ 10 _
S 0.020 0.040 0.51 1.01
MOTOROLA CMOS LOGIC DATA
MC14501UB
5
5 Page | ||
| Páginas | Total 6 Páginas | |
| PDF Descargar | [ Datasheet MC14501BD.PDF ] | |
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