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PDF MC141541P Data sheet ( Hoja de datos )
| Número de pieza | MC141541P | |
| Descripción | Enhanced Monitor On-Screen Display | |
| Fabricantes | Motorola Semiconductors | |
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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Enhanced Monitor On-Screen
Display
CMOS
The MC141541 is a high performance HCMOS device designed to interface
with a microcontroller unit to allow colored symbols or characters to be
displayed on a color monitor. The on–chip PLL allows both multi–system
operation and self–generation of system timing. It also minimizes the MCU’s
burden through its built–in 273 bytes display/control RAM. By storing a full
screen of data and control information, this device has the capability to carry out
‘screen–refresh’ without MCU supervision.
Since there is no spacing between characters, special graphics–oriented
characters can be generated by combining two or more character blocks. There
are two different resolutions that users can choose. By changing the number of
dots per horizontal line to 320 (CGA) or 480 (EGA), smaller characters with
higher resolution can be easily achieved.
Special functions such as character bordering or shadowing, multi–level
windows, double height and double width, and programmable vertical length of
character can also be incorporated. Furthermore, neither massive information
update nor extremely high data transmission rate are expected for normal on–
screen display operation, and serial protocols are implemented in lieu of any
parallel formats to achieve minimum pin count.
A special feature, character RAM fonts, is implemented in this MOSD
enhanced version (EMOSD). Users can download their own fonts and display
them at any time once the chip is powered on. There are two ways for users to
build and store fonts. One is a conventional approach to have masked ROM
fonts. A newer approach is to store the fonts in the EPROM accessed by the
MCU and then download them into the EMOSD character RAM. With this new
technique, users have more flexibility in preparing their fonts and the effective
number of fonts is greatly increased.
• Two Selectable Resolutions: 320 (CGA) and 480 (EGA) Dots per Line
• Fully Programmable Character Array of 10 Rows by 24 Columns
• 273 Bytes Direct Mapping Display RAM Architecture
• Internal PLL Generates a Wide–Ranged System Clock
• For High–End Monitor Application, Maximum Horizontal Frequency is
110 kHz (52.8 MHz Dot Clock at 480 Mode)
• Programmable Vertical Height of Character to Meet Multi–Sync
Requirement
• Programmable Vertical and Horizontal Positioning for Display Center
• 120 Characters and Graphic Symbols ROM and Eight Programmable
Character RAM
• 10 x 16 Dot Matrix Character
• Character–by–Character Color Selection
• A Maximum of Four Selectable Colors per Row
• Double Character Height and Double Character Width
• Character Bordering or Shadowing
• Three Fully Programmable Background Windows with Overlapping
Capability
• Provides a Clock Output Synchronous to the Incoming H Sync for External
PWM
• M_BUS (IIC) Interface with Address $7A
• Single Positive 5 V Supply
Order this document
by MC141541/D
MC141541
P SUFFIX
PLASTIC DIP
CASE 648
ORDERING INFORMATION
MC141541P Plastic DIP
PIN ASSIGNMENT
VSS(A) 1
VCO 2
RP 3
VDD(A) 4
HFLB 5
SS 6
SDA(MOSI) 7
SCL(SCK) 8
16 VSS
15 R
14 G
13 B
12 FBKG
11
HTONE/
PWMCK
10 VFLB
9 VDD
REV 1
2/97 TN97031200
M©OMTotOoroRlaO, InLcA. 1997
MC141541
1
1 page  
The bottom half of the Block Diagram contains the hard-
ware functions for the entire system. It performs all the
EMOSD functions such as programmable vertical length
(from 16 lines to 63 lines), display clock generation (which is
phase locked to the incoming horizontal sync signal at Pin 5
HFLB), bordering or shadowing, and multiple windowing.
COMMUNICATION PROTOCOLS
M_BUS Serial Communication
This is a two–wire serial communication link that is fully
compatible with the IIC bus system. It consists of an SDA bi-
directional data line and an SCL clock input line. Data is sent
from a transmitter (master) to a receiver (slave) via the SDA
line, and is synchronized with a transmitter clock on the SCL
line at the receiving end. The maximum data rate is limited to
100 kbps and the default chip address is $7A, but is hard-
ware changeable by mask set.
Operating Procedure
Figure 2 shows the M_BUS transmission format. The mas-
ter initiates a transmission routine by generating a start
condition followed by a slave address byte. Once the ad-
dress is properly identified, the slave will respond with an ac-
knowledge signal by pulling the SDA line low during the ninth
SCL clock. Each data byte that follows must be eight bits
long, plus the acknowledge bit, for a total of nine bits. Ap-
propriate row and column address information and display
data can be downloaded sequentially in one of the three
transmission formats described in the Data Transmission
Formats section. In the cases of no acknowlege or comple-
tion of data transfer, the master will generate a stop condition
to terminate the transmission routine. Note that the OSD_EN
bit must be set after all the display information has been sent,
in order to activate the EMOSD circuitry of MC141541 so that
the received information can be displayed.
CHIP ADDRESS
SDA ACK
DATA BYTES
ACK
SCL
1 2–7 8 9
START CONDITION
STOP CONDITION
Figure 2. M_BUS Format
DATA TRANSMISSION FORMATS
In this enhanced version MOSD, both display RAM, con-
trol registers, and character RAM fonts need to be pro-
grammed after power–on. The arrangement of the display
RAM and control registers is on the row–column basis, while
the character RAM is on the segment–line basis. Although
the address basis is different, the data downloading proto-
cols are very similar and will be described in the following
sections.
Display RAM and Control Registers
After the proper identification by the receiving device, a
data train of arbitrary length is transmitted from the master.
There are three transmission formats from (a) to (c) as stated
below. The data train in each sequence consists of row ad-
dress (R), column address (C), and display information (I), as
shown in Figure 3. In format (a), display information data
must be preceded with the corresponding row address and
column address. This format is particularly suitable for updat-
ing small amounts of data between different rows. However,
if the current information byte has the same row address as
the one before, format (b) is recommended.
ÎÎrÎÎowadÎÎdr ÎÎÎÎcÎÎoladdÎÎr ÎÎÎÎinfÎÎo ÎÎÎÎ
Figure 3. Data Packet
For a full–screen pattern change that requires a massive
information update, or during power–up, most of the row and
column addresses of either (a) or (b) formats will be consec-
utive. Therefore, a more efficient data transmission format (c)
should be applied. This sends the RAM starting row and col-
umn addresses once only, and then treats all subsequent
data as display information. The row and column addresses
will be automatically incremented internally for each display
information data from the starting location.
The data transmission formats are:
(a) R – > C – > I – > R – > C – > I – > . . . . . . . . .
(b) R – > C – > I – > C – > I – > C – > I. . . . . . .
(c) R – > C – > I – > I – > I – > . . . . . . . . . . . . .
To differentiate the row and column addresses when trans-
ferring data from master, the MSB (most significant bit) is set,
as in Figure 4: ‘1’ to represent row, and ‘0’ for column ad-
dress. Furthermore, to distinguish the column address be-
tween formats (a), (b), and (c), the sixth bit of the column
address is set to ‘1’ which represents format (c), and ‘0’ for
format (a) or (b). However, there is some limitation on using
mixed formats during a single transmission. It is permissible
to change the format from (a) to (b), or from (a) to (c), or from
(b) to (a), but not from (c) back to (a) or (b).
ADDRESS
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ7
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎROW
1
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎCOLUMN 0
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎCOLUMN 0
BIT
654321
XX X D DD
0 XDDDD
1 XDDDD
FORMAT
0
D a, b, c
D a, b
Dc
X: don’t care
D: valid data
Figure 4. Row & Column Address Bit Patterns
Character RAM
The structure of eight character RAM fonts is shown in Fig-
ure 5. They occupy the font number from 0 to 7. Because of
the 10 x 16 dot matrix font, each font is broken down into two
segments in the horizontal direction and 16 lines in the verti-
cal direction. Therefore, there are five dots that need to be
defined for each specified segment–line location. This 5–bit
data forms the lower five bits of the information data byte and
the higher three bits are ignored. Because there are 16 seg-
ments (two segments per font) and 16 lines, both the seg-
ment and line addresses are four bits wide.
MOTOROLA
MC141541
5
5 Page 
Although there are 24 character display registers that can
be programmed for each row, not every programmed charac-
ter can be shown on the screen in 320–dot resolution. Usual-
ly only 24 characters can be shown in this resolution at most.
This is induced by the time that is required to retrace the H
scan line. At 480–dot resolution, a total of 24 characters can
be displayed on the screen if the horizontal delay register is
set properly.
Figure 13 illustrates the timing of all output signals as a
function of window and fast–blanking features. Line 3 of all
three characters is used to illustrate the timing signals. The
shaded area depicts the window area. The characters on the
left and right appear identical except for the FBKGC bit. The
middle character does not have a window as its background.
Notice that signal HTONE/PWMCK is active only in the win-
dow area. Timing of the signal FBKG depends on the config-
uration of the FBKGC bit. The configuration of the FBKGC bit
affects only the FBKG signal timing; it has no effect on the
timing of HTONE/PWMCK. Waveform ‘R, G, or B’, which is
the actual waveform at R, G, or B pin, is the logical OR of
waveform ‘character R, G, or B’ and waveform ‘window R, G,
or B’. ‘Character R, G, or B’ and ‘window R, G, or B’ are inter-
nal signals for illustration purpose only. Also notice that
HTONE/PWMCK has exactly the same waveform as ‘win-
dow R, G, or B’.
ÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌ
ÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌ
FONT
Icon Combination
MC141541 contains 120–character ROM and eight RAM.
The user can create an on–screen menu based on those
characters and programmable RAM. Refer to Table 3 for icon
combinations.
Table 3. Combination Map
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎICON
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎVolume Bar I
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎVolume Bar II
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎSize
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎPosition
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎGeometry
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎContrast
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎBrightness
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎHorizontal Position
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎHorizontal Sizing
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎVertical Position
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎVertical Sizing
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎPin Cushion
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎDeguassing
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎTrapezoid
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎParallelogram
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎColor Select
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎVideo Level
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎInput Select
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎRecall
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎSave
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎLeft/Right Arrows
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎINC/DEC sign
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎSpeaker
ROM ADDRESS (HEX)
48, 49, 57
47
4F, 50
51, 52
53, 54, 55, 56
58,59
5A, 5B
5C, 5D
5E, 5F
60, 61
62, 63
64, 65
66, 67
6C, 6D, 6E, 6F
68, 69, 6A, 6B
70, 71
72, 73
74, 75
76,77
78, 79
7A, 7B
7C, 7D
7E, 7F
ROM CONTENT
Figures 14 – 17 show the ROM content of MC141541.
Figure 13. Timing of Output Signals as a Function
of Window and FBKGC Bit Features
MOTOROLA
MC141541
11
11 Page | ||
| Páginas | Total 16 Páginas | |
| PDF Descargar | [ Datasheet MC141541P.PDF ] | |
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