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PDF MC14024B Data sheet ( Hoja de datos )
| Número de pieza | MC14024B | |
| Descripción | 7-Stage Ripple Counter | |
| Fabricantes | ON Semiconductor | |
| Logotipo |  |
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MC14024B
7-Stage Ripple Counter
The MC14024B is a 7−stage ripple counter with short propagation
delays and high maximum clock rates. The Reset input has standard
noise immunity, however the Clock input has increased noise
immunity due to Hysteresis. The output of each counter stage is
buffered.
Features
• Diode Protection on All Inputs
• Output Transitions Occur on the Falling Edge of the Clock Pulse
• Supply Voltage Range = 3.0 Vdc to 18 Vdc
• Capable of Driving Two Low−power TTL Loads or One Low−power
Schottky TTL Load Over the Rated Temperature Range
• Pin−for−Pin Replacement for CD4024B
• NLV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AEC−Q100
Qualified and PPAP Capable
• This Device is Pb−Free and is RoHS Compliant
MAXIMUM RATINGS (Voltages Referenced to VSS)
Symbol
Parameter
Value
Unit
VDD
Vin, Vout
DC Supply Voltage Range
Input or Output Voltage Range
(DC or Transient)
−0.5 to +18.0
−0.5 to VDD + 0.5
V
V
Iin, Iout
Input or Output Current
(DC or Transient) per Pin
±10 mA
PD Power Dissipation, per Package
(Note 1)
500 mW
TA Ambient Temperature Range
Tstg Storage Temperature Range
TL Lead Temperature
(8−Second Soldering)
−55 to +125
−65 to +150
260
°C
°C
°C
Stresses exceeding those listed in the Maximum Ratings table may damage the
device. If any of these limits are exceeded, device functionality should not be
assumed, damage may occur and reliability may be affected.
1. Temperature Derating: “D/DW” Packages: –7.0 mW/_C From 65_C To 125_C
This device contains protection circuitry to guard against damage due to high
static voltages or electric fields. However, precautions must be taken to avoid
applications of any voltage higher than maximum rated voltages to this
high−impedance circuit. For proper operation, Vin and Vout should be constrained
to the range VSS ≤ (Vin or Vout) ≤ VDD.
Unused inputs must always be tied to an appropriate logic voltage level
(e.g., either VSS or VDD). Unused outputs must be left open.
http://onsemi.com
SOIC−14
D SUFFIX
CASE 751A
PIN ASSIGNMENT
CLOCK
RESET
Q7
Q6
1
2
3
4
14 VDD
13 NC
12 Q1
11 Q2
Q5 5
Q4 6
10 NC
9 Q3
VSS 7
8 NC
VDD = PIN 14
VSS = PIN 7
NC = NO CONNECTION
MARKING DIAGRAM
14
14024BG
AWLYWW
1
A
WL, L
YY, Y
WW, W
G
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 2 of this data sheet.
© Semiconductor Components Industries, LLC, 2014
August, 2014 − Rev. 10
1
Publication Order Number:
MC14024B/D
1 page  
MC14024B
VDD
VDD
VOL = Vout
C Qn
R
IOH
EXTERNAL
COUNT Qn TO A VSS
LOGIC “1" LEVEL.
POWER
SUPPLY
Figure 1. Typical Output Source
Characteristics Test Circuit
VDD VOH = Vout
C Qn
R
VSS
IOL
EXTERNAL
POWER
SUPPLY
Figure 2. Typical Output Sink
Characteristics Test Circuit
500 mF
VDD
0.01 mF
ID CERAMIC
PULSE
GENERATOR
f
C Q1
Q2
Q3
Q4
Q5
Q6
R Q7
CL
CL
CL
CL
CL
CL
CL
VSS
Figure 3. Power Dissipation Test Circuit
http://onsemi.com
5
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| Páginas | Total 7 Páginas | |
| PDF Descargar | [ Datasheet MC14024B.PDF ] | |
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