Datenblatt-pdf.com


MC14021BFEL Schematic ( PDF Datasheet ) - ON Semiconductor

Teilenummer MC14021BFEL
Beschreibung 8-Bit Static Shift Register
Hersteller ON Semiconductor
Logo ON Semiconductor Logo 




Gesamt 8 Seiten
MC14021BFEL Datasheet, Funktion
MC14014B, MC14021B
8-Bit Static Shift Register
The MC14014B and MC14021B 8–bit static shift registers are
constructed with MOS P–channel and N–channel enhancement mode
devices in a single monolithic structure. These shift registers find
primary use in parallel–to–serial data conversion, synchronous and
asynchronous parallel input, serial output data queueing; and other
general purpose register applications requiring low power and/or high
noise immunity.
Synchronous Parallel Input/Serial Output (MC14014B)
Asynchronous Parallel Input/Serial Output (MC14021B)
Synchronous Serial Input/Serial Output
Full Static Operation
“Q” Outputs from Sixth, Seventh, and Eighth Stages
Double Diode Input Protection
Supply Voltage Range = 3.0 Vdc to 18 Vdc
Capable of Driving Two Low–power TTL Loads or One Low–power
Schottky TTL Load Over the Rated Temperature Range
MC14014B Pin–for–Pin Replacement for CD4014B
MC14021B Pin–for–Pin Replacement for CD4021B
MAXIMUM RATINGS (Voltages Referenced to VSS) (Note 2.)
Symbol
Parameter
Value
VDD
Vin, Vout
DC Supply Voltage Range
Input or Output Voltage Range
(DC or Transient)
– 0.5 to +18.0
– 0.5 to VDD + 0.5
Unit
V
V
Iin, Iout
Input or Output Current
(DC or Transient) per Pin
± 10 mA
PD Power Dissipation,
per Package (Note 3.)
500 mW
TA Ambient Temperature Range
Tstg Storage Temperature Range
TL Lead Temperature
(8–Second Soldering)
– 55 to +125
– 65 to +150
260
°C
°C
°C
2. Maximum Ratings are those values beyond which damage to the device
may occur.
3. Temperature Derating:
Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C
This device contains protection circuitry to guard against damage due to high
static voltages or electric fields. However, precautions must be taken to avoid
applications of any voltage higher than maximum rated voltages to this
v vhigh–impedance circuit. For proper operation, Vin and Vout should be constrained
to the range VSS (Vin or Vout) VDD.
Unused inputs must always be tied to an appropriate logic voltage level (e.g.,
either VSS or VDD). Unused outputs must be left open.
http://onsemi.com
PDIP–16
P SUFFIX
CASE 648
MARKING
DIAGRAMS
16
MC140XXBCP
AWLYYWW
1
SOIC–16
D SUFFIX
CASE 751B
16
140XXB
AWLYWW
1
SOEIAJ–16
F SUFFIX
CASE 966
16
MC140XXB
AWLYWW
1
XX = Specific Device Code
A = Assembly Location
WL or L = Wafer Lot
YY or Y = Year
WW or W = Work Week
ORDERING INFORMATION
Device
Package
Shipping
MC14014BCP
PDIP–16
2000/Box
MC14014BD
SOIC–16
48/Rail
MC14014BDR2 SOIC–16 2500/Tape & Reel
MC14014BF
SOEIAJ–16 See Note 1.
MC14014BFEL SOEIAJ–16 See Note 1.
MC14021BCP
PDIP–16
2000/Box
MC14021BD
SOIC–16
48/Rail
MC14021BDR2 SOIC–16 2500/Tape & Reel
MC14021BF
SOEIAJ–16 See Note 1.
MC14021BFEL SOEIAJ–16 See Note 1.
1. For ordering information on the EIAJ version of
the SOIC packages, please contact your local
ON Semiconductor representative.
© Semiconductor Components Industries, LLC, 2000
March, 2000 – Rev. 3
1
Publication Order Number:
MC14014B/D






MC14021BFEL Datasheet, Funktion
MC14014B, MC14021B
PACKAGE DIMENSIONS
–A–
16
1
H
G
9
B
8
PDIP–16
P SUFFIX
PLASTIC DIP PACKAGE
CASE 648–08
ISSUE R
FC
S
L
–T–
SEATING
PLANE
KJ
D 16 PL
0.25 (0.010) M T A M
M
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.
5. ROUNDED CORNERS OPTIONAL.
INCHES
MILLIMETERS
DIM MIN MAX MIN MAX
A 0.740 0.770 18.80 19.55
B 0.250 0.270 6.35 6.85
C 0.145 0.175 3.69 4.44
D 0.015 0.021 0.39 0.53
F 0.040 0.70 1.02 1.77
G 0.100 BSC
2.54 BSC
H 0.050 BSC
1.27 BSC
J 0.008 0.015 0.21 0.38
K 0.110 0.130 2.80 3.30
L 0.295 0.305 7.50 7.74
M 0_ 10_ 0_ 10 _
S 0.020 0.040 0.51 1.01
–A–
16
1
SOIC–16
D SUFFIX
PLASTIC SOIC PACKAGE
CASE 751B–05
ISSUE J
9
–B– P 8 PL
8 0.25 (0.010) M B S
G
–T– SEATING
PLANE
K
C
D 16 PL
0.25 (0.010) M T B S A S
R X 45_
F
MJ
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
MILLIMETERS
INCHES
DIM MIN MAX MIN MAX
A 9.80 10.00 0.386 0.393
B 3.80 4.00 0.150 0.157
C 1.35 1.75 0.054 0.068
D 0.35 0.49 0.014 0.019
F 0.40 1.25 0.016 0.049
G 1.27 BSC
0.050 BSC
J 0.19 0.25 0.008 0.009
K 0.10 0.25 0.004 0.009
M 0_ 7_ 0_ 7_
P 5.80 6.20 0.229 0.244
R 0.25 0.50 0.010 0.019
http://onsemi.com
6

6 Page







SeitenGesamt 8 Seiten
PDF Download[ MC14021BFEL Schematic.PDF ]

Link teilen




Besondere Datenblatt

TeilenummerBeschreibungHersteller
MC14021BFEL8-Bit Static Shift RegisterON Semiconductor
ON Semiconductor

TeilenummerBeschreibungHersteller
CD40175BC

Hex D-Type Flip-Flop / Quad D-Type Flip-Flop.

Fairchild Semiconductor
Fairchild Semiconductor
KTD1146

EPITAXIAL PLANAR NPN TRANSISTOR.

KEC
KEC


www.Datenblatt-PDF.com       |      2020       |      Kontakt     |      Suche