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PDF MC14016B Data sheet ( Hoja de datos )
| Número de pieza | MC14016B | |
| Descripción | Quad Analog Switch / Quad Multiplexer | |
| Fabricantes | ON Semiconductor | |
| Logotipo |  |
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MC14016B
Quad Analog Switch/
Quad Multiplexer
The MC14016B quad bilateral switch is constructed with MOS
P−channel and N−channel enhancement mode devices in a single
monolithic structure. Each MC14016B consists of four independent
switches capable of controlling either digital or analog signals.
The quad bilateral switch is used in signal gating, chopper, modulator,
demodulator and CMOS logic implementation.
Features
• Diode Protection on All Inputs
• Supply Voltage Range = 3.0 Vdc to 18 Vdc
• Linearized Transfer Characteristics
• Low Noise − 12 nV/√Cycle, f ≥ 1.0 kHz typical
• Pin−for−Pin Replacements for CD4016B, CD4066B (Note Improved
Transfer Characteristic Design Causes More Parasitic Coupling
Capacitance than CD4016)
• For Lower RON, Use The HC4016 High−Speed CMOS Device or
The MC14066B
• This Device Has Inputs and Outputs Which Do Not Have ESD
Protection. Antistatic Precautions Must Be Taken
• NLV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AEC−Q100
Qualified and PPAP Capable
• These Devices are Pb−Free and are RoHS Compliant
MAXIMUM RATINGS (Voltages Referenced to VSS)
Symbol
Parameter
Value
Unit
VDD
Vin, Vout
DC Supply Voltage Range
Input or Output Voltage Range
(DC or Transient)
−0.5 to +18.0
−0.5 to VDD + 0.5
V
V
Iin Input Current (DC or Transient)
per Control Pin
±10 mA
ISW Switch Through Current
PD Power Dissipation, per Package
(Note 1)
±25 mA
500 mW
TA Ambient Temperature Range
Tstg Storage Temperature Range
TL Lead Temperature
(8−Second Soldering)
−55 to +125
−65 to +150
260
°C
°C
°C
Stresses exceeding those listed in the Maximum Ratings table may damage the
device. If any of these limits are exceeded, device functionality should not be
assumed, damage may occur and reliability may be affected.
1. Temperature Derating: “D/DW” Packages: –7.0 mW/_C From 65_C To 125_C
This device contains protection circuitry to guard against damage due to high
static voltages or electric fields. However, precautions must be taken to avoid
applications of any voltage higher than maximum rated voltages to this
high−impedance circuit. For proper operation, Vin and Vout should be constrained
to the range VSS ≤ (Vin or Vout) ≤ VDD.
Unused inputs must always be tied to an appropriate logic voltage level
(e.g., either VSS or VDD). Unused outputs must be left open.
http://onsemi.com
SOIC−14
D SUFFIX
CASE 751A
SOEIAJ−14
F SUFFIX
CASE 965
MARKING DIAGRAMS
14
14016BG
AWLYWW
1
SOIC−14
14
MC14016B
ALYWG
1
SOEIAJ−14
A
WL, L
YY, Y
WW, W
G
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Indicator
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 2 of this data sheet.
© Semiconductor Components Industries, LLC, 2014
July, 2014 − Rev. 11
1
Publication Order Number:
MC14016B/D
1 page  
MC14016B
VC IS
Vin Vout
VIL: VC is raised from VSS until VC = VIL.
VIL: at VC = VIL: IS = ±10 mA with Vin = VSS, Vout = VDD or Vin = VDD, Vout = VSS.
VIH: When VC = VIH to VDD, the switch is ON and the RON specifications are met.
Figure 1. Input Voltage Test Circuit
VDD
ID
PULSE
GENERATOR
VDD Vout
TO ALL
4 CIRCUITS CONTROL
fc INPUT
PD = VDD x ID
VSS Vin
10 k
Figure 2. Quiescent Power Dissipation
Test Circuit
10,000
1000
100
TA = 25°C
VDD = 15 Vdc
10 Vdc
5.0 Vdc
10
1.0
5.0 k 10 k
100 k
1.0 M
fc, FREQUENCY (Hz)
10 M 50 M
Figure 3. Typical Power Dissipation per Circuit
(1/4 of device shown)
TYPICAL RON versus INPUT VOLTAGE
700
VSS = 0 Vdc
600 RL = 10 kW
TA = 25°C
500
400
VC = VDD = 10 Vdc
300
200 VC = VDD = 15 Vdc
100
0
0 2.0
6.0 10
14
Vin, INPUT VOLTAGE (Vdc)
Figure 4. VSS = 0 V
18 20
http://onsemi.com
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