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PDF MC10H681 Data sheet ( Hoja de datos )
| Número de pieza | MC10H681 | |
| Descripción | Hex ECL/TTL Transceiver with Latches | |
| Fabricantes | ON Semiconductor | |
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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Hex ECLā/āTTL Transceiver
with Latches
The MC10/100H681 is a dual supply Hex ECL/TTL transceiver with
latches in both directions. ECL controlled Direction and Chip Enable Bar
pins. There are two Latch Enable pins, one for each direction.
The ECL outputs are single ended and drive 50 Ω. The TTL outputs are
specified to source 15 mA and sink 48 mA, allowing the ability to drive highly
capacitive loads. The high driving ability of the TTL outputs make the device
ideal for bussing applications.
The ECL output levels are standard VOH and VOL cutoff equal to –2.0 V
(VTT). When the ECL ports are disabled the outputs go to the VOL cutoff
level. Multiple ECL VCCO pins are utilized to minimize switching noise.
The TTL ports have standard levels. The TTL input receivers have PNP
input devices to significantly reduce loading. Multiple TTL power and ground
pins are utilized to minimize switching noise.
The 10H version is compatible with MECL 10H ECL logic levels. The
100H version is compatible with 100K levels.
• Separate Latch Enable Controls for each Direction
• ECL Single Ended 50 Ω I/O Port
• High Drive TTL I/O Ports
• Extra TTL and ECL Power/Ground Pins to Minimize
Switching Noise
• Dual Supply
• Direction and Chip Enable Control Pins
Pinout: 28–Lead PLCC (Top View)
25 24 23 22 21 20 19
TIO2 26
18
VT 27
GT 28
17
16
EIO5
VCCO
EIO4
TIO1 1
VT 2
15 VCCE
14 EIO3
GT 3
13 VCCO
TIO0 4
12 EIO2
5 6 7 8 9 10 11
Pin Symbol
1 TI01
2 VT
3 GT
4 TI00
5 DIR
6 CEB
7 LEET
8 LETE
9 VEE
10 EI00
11 EI01
12 EI02
13 VCCO
14 EIO3
15 VCCE
16 EIO4
17 VCCO
18 EIO5
19 TI05
20 GT
21 VT
22 TI04
23 GT
24 VT
25 TIO3
26 TIO2
27 VT
28 GT
MC10H681
MC100H681
FN SUFFIX
PLASTIC PACKAGE
CASE 776–02
Description
TTL I/O BIT 1
TTL VCC (5.0 V)
TTL GND (0 V)
TTL I/O Bit 0
Direction Control (ECL)
Chip Enable Bar Control (ECL)
Latch Enable ECL-TTL Control (ECL)
Latch Enable TTL-ECL Control (ECL)
ECL Supply (– 5.2 /– 4.5 V)
ECL I/O BIT 0
ECL I/O BIT 1
ECL I/O BIT 2
ECL VCC (0 V) — Outputs
TTL I/O BIT 3
ECL VCC (0 V)
ECL I/O BIT 4
ECL VCC (0 V) — Outputs
ECL I/O BIT 5
TTL I/O BIT 5
TTL GND (0 V)
TTL VCC (5.0 V)
TTL I/O BIT 4
TTL GND (0 V)
TTL VCC (5.0 V)
TTL I/O BIT 3
TTL I/O BIT 2
TTL VCC (5.0 V)
TTL VCC (0 V)
9/96
© Motorola, Inc. 1996
2–316
REV 2
1 page  
MC10H681 MC100H681
ECL
USE 0.1 µF CAPACITORS
FOR DECOUPLING.
PULSE
GENERATOR
50 Ω COAX
TEST CIRCUITS AND WAVEFORMS
VEE VCC & VCCO
TTL
IN
DEVICE
UNDER
TEST
OUT
+7 V
tPZL, tPLZ
O,C
USE OSCILLOSCOPE
INTERNAL 50 Ω LOAD
FOR TERMINATION.
CH A CH B
OSCILLOSCOPE
DEVICE
UNDER
TEST
50 pF
OPEN
ALL
OTHERS
R1
500 Ω
R2
500 Ω
Figure 1. Test Circuit ECL
Figure 2. Test Circuit TTL
ECL/TTL
VOUT
80%/2.0 V
20%/1.0 V
TRISE
TFALL
Figure 3. Rise and Fall Times
ECL/TTL
50%/1.5 V
VIN
VOUT
TPD++
50%/1.5 V
TPD – –
Figure 4. Propagation Delay — Single Ended
TTL
VE
VE
VOUT
1.5 V
TPZL
1.5 V
1.5 V
TPLZ
VOL
0.3 V
Figure 5. 3-State Output Low Enable
and Disable Times
TTL
VE
VE
VOUT
1.5 V
TPZL
1.5 V
1.5 V
TPHZ
0.3 V
>VOH≈
3.5 V
Figure 6. 3-State Output High Enable
and Disable Times
MOTOROLA
2–320
MECL Data
DL122 — Rev 6
5 Page | ||
| Páginas | Total 7 Páginas | |
| PDF Descargar | [ Datasheet MC10H681.PDF ] | |
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