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PDF MC10H646 Data sheet ( Hoja de datos )
| Número de pieza | MC10H646 | |
| Descripción | PENTIUM MICROPROCESSOR PECL/TTL-TTL CLOCK DRIVER | |
| Fabricantes | ON Semiconductor | |
| Logotipo |  |
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MC10H646, MC100H646
PECL/TTL−TTL 1:8 Clock
Distribution Chip
Description
The MC10H/100H646 is a single supply, low skew translating 1:8
clock driver. Devices in the ON Semiconductor H646 translator series
utilize the 28−lead PLCC for optimal power pinning, signal flow
through and electrical performance. The single supply H646 is similar
to the H643, which is a dual supply 1:8 version of the same function.
The H646 was designed specifically to drive series terminated
transmission lines. Special techniques were used to match the HIGH
and LOW output impedances to about 7.0 W. This simplifies the
choice of the termination resistor for series terminated applications. To
match the HIGH and LOW output impedances, it was necessary to
remove the standard IOS limiting resistor. As a result, the user should
take care in preventing an output short to ground as the part will be
permanently damaged.
The H646 device meets all of the requirements for driving the
60 MHz and 66 MHz Intel Pentium® Microprocessor. The device has
no PLL components, which greatly simplifies its implementation into
a digital design. The eight copies of the clock allows for
point−to−point clock distribution to simplify board layout and
optimize signal integrity.
The H646 provides differential PECL inputs for picking up LOW
skew PECL clocks from the backplane and distributing it to TTL loads
on a daughter board. When used in conjunction with the
MC10/100E111, very low skew, very wide clock trees can be
designed. In addition, a TTL level clock input is provided for
flexibility. Note that only one of the inputs can be used on a single
chip. For correct operation, the unused input pins should be left open.
The Output Enable pin forces the outputs into a high impedance
state when a logic 0 is applied.
The output buffers of the H646 can drive two series terminated,
50 W transmission lines each. This capability allows the H646 to drive
up to 16 different point−to−point clock loads. Refer to the
Applications section for a more detailed discussion in this area.
The 10H version is compatible with MECL™ 10H ECL logic levels.
The 100H version is compatible with 100K levels.
http://onsemi.com
PLCC−28
FN SUFFIX
CASE 776
MARKING DIAGRAM*
1
MCxxxH646G
AWLYYWW
xxx = 10 or 100
A = Assembly Location
WL = Wafer Lot
YY = Year
WW = Work Week
G = Pb−Free Package
*For additional marking information, refer to
Application Note AND8002/D.
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 5 of this data sheet.
Features
• PECL/TTL−TTL Version of Popular ECLinPS™ E111
• Low Skew
• Guaranteed Skew Spec
• Tri−State Enable
• Differential Internal Design
• VBB Output
• Single Supply
• Extra TTL and ECL Power/Ground Pins
• Matched High and Low Output Impedance
• Meets Specifications Required to Drive
Intel® Pentium® Microprocessors
• Pb−Free Packages are Available*
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
© Semiconductor Components Industries, LLC, 2006
November, 2006 − Rev. 5
1
Publication Order Number:
MC10H646/D
1 page  
MC10H646, MC100H646
Table 8. AC CHARACTERISTICS (IVT = OVT = VCCE = 5.0 V ±5%)
0°C
25°C
85°C
Symbol
Characteristic
Condition
Min Max Min Max Min Max Unit
tPLH Propagation Delay
ECLK to Q
TCLK to Q
4.8 5.8 5.0 6.0 5.6 6.6 ns
5.1 6.4 5.3 6.4 5.7 7.0
tPHL Propagation Delay
ECLK to Q
TCLK to Q
4.4 5.4 4.4 5.4 4.8 5.8 ns
4.7 6.0 4.8 5.9 5.2 6.5
tSK(O)
Output Skew
Q0, Q3, Q4, Q7
Q1, Q2, Q5
Q0−Q7
(Notes 4, 9)
350 350 350 ps
350 350 350
500 500 500
tSK(PR) Process Skew
ECLK to Q
TCLK to Q
(Notes 5, 9)
1.0 1.0 1.0 ns
1.3 1.1 1.3
tSK(P)
tr, tf
tPW
Pulse Skew
Rise/Fall Time
Output Pulse Width
DtPLH − tPHL
66 MHz @ 2.0 V
66 MHz @ 0.8 V
60 MHz @ 2.0 V
60 MHz @ 0.8 V
(Notes 6, 9)
1.0 1.0 1.0 ns
0.3 1.5 0.3 1.5 0.3 1.5 ns
5.5 5.5 5.5 ns
5.5 5.5 5.5
6.0 6.0 6.0
6.0 6.0 6.0
tStability Clock Stability
(Notes 7, 9)
$75
$75
$75 ps
FMAX
Maximum Input Frequency
(Notes 8, 9)
80 80 80 MHz
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification
limit values are applied individually under normal operating conditions and not valid simultaneously.
4. Output skew defined for identical output transitions.
5. Process skew is valid for VCC = 5.0 V ± 5%.
6. Parameters guaranteed by tSK(P) and tr, tf specification limits.
7. Clock stability is the period variation between two successive rising edges.
8. For series terminated lines. See Applications section for FMAX enhancement techniques.
9. All AC specifications tested driving 50 W series terminated transmission lines at 80 MHz.
ORDERING INFORMATION
Device
Package
Shipping†
MC10H646FN
PLCC−28
37 Units / Rail
MC10H646FNG
PLCC−28
(Pb−Free)
37 Units / Rail
MC10H646FNR2
PLCC−28
500 / Tape & Reel
MC10H646FNR2G
PLCC−28
(Pb−Free)
500 / Tape & Reel
MC100H646FN
PLCC−28
37 Units / Rail
MC100H646FNG
PLCC−28
(Pb−Free)
37 Units / Rail
MC100H646FNR2
PLCC−28
500 / Tape & Reel
MC100H646FNR2G
PLCC−28
(Pb−Free)
500 / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
http://onsemi.com
5
5 Page | ||
| Páginas | Total 8 Páginas | |
| PDF Descargar | [ Datasheet MC10H646.PDF ] | |
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