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PDF MC10E445 Data sheet ( Hoja de datos )
| Número de pieza | MC10E445 | |
| Descripción | 4-BIT SERIAL/ PARALLEL CONVERTER | |
| Fabricantes | ON Semiconductor | |
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MC10E445, MC100E445
5V ECL 4-Bit Serial/Parallel
Converter
Description
The MC10/100E445 is an integrated 4-bit serial to parallel data
converter. The device is designed to operate for NRZ data rates of up to
2.0 Gb/s. The chip generates a divide by 4 and a divide by 8 clock for
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both 4-bit conversion and a two chip 8-bit conversion function. The
conversion sequence was chosen to convert the first serial bit to Q0, the
second to Q1 etc.
PLCC−28
Two selectable serial inputs provide a loopback capability for testing
FN SUFFIX
purposes when the device is used in conjunction with the E446 parallel to
CASE 776
serial converter.
The start bit for conversion can be moved using the SYNC input. A
single pulse applied asynchronously for at least two input clock cycles
shifts the start bit for conversion from Qn to Qn−1. For each additional
MARKING DIAGRAM*
shift required an additional pulse must be applied to the SYNC input.
1 28
Asserting the SYNC input will force the internal clock dividers to
“swallow” a clock pulse, effectively shifting a bit from the Qn to the Qn−1
output (see Timing Diagram B).
The MODE input is used to select the conversion mode of the device.
With the MODE input LOW, or open, the device will function as a 4-bit
MCxxxE445FNG
AWLYYWW
converter. When the mode input is driven HIGH the data on the output will
change on every eighth clock cycle thus allowing for an 8-bit conversion
scheme using two E445’s. When cascaded in an 8-bit conversion scheme
xxx = 10 or 100
the devices will not operate at the 2.0 Gb/s data rate of a single device.
Refer to the applications section of this data sheet for more information on
cascading the E445.
Upon power-up the internal flip-flops will attain a random state. To
synchronize multiple E445’s in a system the master reset must be asserted.
A = Assembly Location
WL = Wafer Lot
YY = Year
WW = Work Week
G = Pb−Free Package
The VBB pin, an internally generated voltage supply, is available to this
device only. For single-ended input conditions, the unused differential
input is connected to VBB as a switching reference voltage. VBB may also
rebias AC coupled inputs. When used, decouple VBB and VCC via a
0.01 mF capacitor and limit current sourcing or sinking to 0.5 mA. When
not used, VBB should be left open.
The 100 Series contains temperature compensation.
*For additional marking information, refer to
Application Note AND8002/D.
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 11 of this data sheet.
Features
• On-Chip Clock ÷4 and ÷8
• ESD Protection: Human Body Model; > 2 kV,
Machine Model; > 100 V
• 2.0 Gb/s Data Rate Capability
• Meets or Exceeds JEDEC Spec EIA/JESD78
• Differential Clock and Serial Inputs
IC Latchup Test
• VBB Output for Single-Ended Input Applications
• Asynchronous Data Synchronization
• Mode Select to Expand to 8-Bits
• PECL Mode Operating Range: VCC = 4.2 V to 5.7 V
with VEE = 0 V
• NECL Mode Operating Range: VCC = 0 V
with VEE = −4.2 V to −5.7 V
• Internal Input 50 kW Pulldown Resistors
• Moisture Sensitivity Level: Pb = 1; Pb−Free = 3
For Additional Information, see Application Note
AND8003/D
• Flammability Rating: UL 94 V−0 @ 0.125 in,
Oxygen Index: 28 to 34
• Transistor Count = 528 devices
• PECL Mode Operating Range: VCC = 4.2 V to 5.7 V
with VEE = 0 V
• Pb−Free Packages are Available*
*For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting
Techniques Reference Manual, SOLDERRM/D.
© Semiconductor Components Industries, LLC, 2006
November, 2006 − Rev. 12
1
Publication Order Number:
MC10E445/D
1 page  
MC10E445, MC100E445
Table 4. 10E SERIES PECL DC CHARACTERISTICS VCCx = 5.0 V; VEE = 0.0 V (Note 1)
0°C 25°C
85°C
Symbol
Characteristic
Min Typ Max Min Typ Max Min Typ Max Unit
IEE
VOH
VOHsout
VOL
VIH
VIL
VBB
VIHCMR
Power Supply Current
Output HIGH Voltage (Note 2)
Output HIGH Voltage sout/sout
Output LOW Voltage (Note 2)
Input HIGH Voltage (Single−Ended)
Input LOW Voltage (Single−Ended)
Output Voltage Reference
Input HIGH Voltage Common Mode
Range (Differential Configuration)
(Note 3)
3980
3975
3050
3830
3050
3.62
2.2
154
4070
3210
3995
3285
185
4160
4170
3370
4160
3520
3.74
4.6
4020
3975
3050
3870
3050
3.65
2.2
154
4105
3210
4030
3285
185
4190
4170
3370
4190
3520
3.75
4.6
4090
3975
3050
3940
3050
3.69
2.2
154
4185
3227
4110
3302
185
4280
4170
3405
4280
3555
3.81
4.6
mA
mV
mV
mV
mV
mV
V
V
IIH Input HIGH Current
150 150 150 mA
IIL Input LOW Current
0.5 0.3
0.5 0.25
0.3 0.2
mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
1. Input and output parameters vary 1:1 with VCC. VEE can vary −0.46 V / +0.06 V.
2. Outputs are terminated through a 50 W resistor to VCC − 2.0 V.
3. VIHCMR min varies 1:1 with VEE, max varies 1:1 with VCC.
Table 5. 10E SERIES NECL DC CHARACTERISTICS VCCx = 0.0 V; VEE = −5.0 V (Note 4)
0°C 25°C
85°C
Symbol
Characteristic
Min Typ Max Min Typ Max Min Typ Max Unit
IEE
VOH
VOHsout
VOL
VIH
VIL
VBB
VIHCMR
Power Supply Current
Output HIGH Voltage (Note 5)
Output HIGH Voltage sout/sout
Output LOW Voltage (Note 5)
Input HIGH Voltage (Single−Ended)
Input LOW Voltage (Single−Ended)
Output Voltage Reference
Input HIGH Voltage Common Mode
Range (Differential Configuration)
(Note 6)
154 185
154 185
154 185
−1020 −930 −840 −980 −895 −810 −910 −815 −720
−1025
−830 −1025
−830 −1025
−830
−1950 −1790 −1630 −1950 −1790 −1630 −1950 −1773 −1595
−1170 −1005 −840 −1130 −970 −810 −1060 −970 −720
−1950 −1715 −1480 −1950 −1715 −1480 −1950 −1698 −1445
−1.38
−1.27 −1.35
−1.25 −1.31
−1.19
−2.8 −0.4 −2.8 −0.4 −2.8 −0.4
mA
mV
mV
mV
mV
mV
V
V
IIH Input HIGH Current
150 150 150 mA
IIL Input LOW Current
0.5 0.3
0.5 0.065
0.3 0.2
mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
4. Input and output parameters vary 1:1 with VCC. VEE can vary −0.46 V / +0.06 V.
5. Outputs are terminated through a 50 W resistor to VCC − 2.0 V.
6. VIHCMR min varies 1:1 with VEE, max varies 1:1 with VCC.
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5
5 Page 
MC10E445, MC100E445
Driver
Device
Q
Q
Zo = 50 W
Zo = 50 W
50 W
50 W
D
Receiver
Device
D
VTT
VTT = VCC − 2.0 V
Figure 10. Typical Termination for Output Driver and Device Evaluation
(See Application Note AND8020/D − Termination of ECL Logic Devices.)
ORDERING INFORMATION
Device
Package
Shipping†
MC10E445FN
PLCC−28
37 Units / Rail
MC10E445FNG
PLCC−28
(Pb−Free)
37 Units / Rail
MC10E445FNR2
PLCC−28
500 / Tape & Reel
MC10E445FNR2G
PLCC−28
(Pb−Free)
500 / Tape & Reel
MC100E445FN
PLCC−28
37 Units / Rail
MC100E445FNG
PLCC−28
(Pb−Free)
37 Units / Rail
MC100E445FNR2
PLCC−28
500 / Tape & Reel
MC100E445FNR2G
PLCC−28
(Pb−Free)
500 / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
Resource Reference of Application Notes
AN1405/D − ECL Clock Distribution Techniques
AN1406/D − Designing with PECL (ECL at +5.0 V)
AN1503/D − ECLinPSt I/O SPiCE Modeling Kit
AN1504/D − Metastability and the ECLinPS Family
AN1568/D − Interfacing Between LVDS and ECL
AN1672/D − The ECL Translator Guide
AND8001/D − Odd Number Counters Design
AND8002/D − Marking and Date Codes
AND8020/D − Termination of ECL Logic Devices
AND8066/D − Interfacing with ECLinPS
AND8090/D − AC Characteristics of ECL Devices
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11
11 Page | ||
| Páginas | Total 13 Páginas | |
| PDF Descargar | [ Datasheet MC10E445.PDF ] | |
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