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PDF MC10E212 Data sheet ( Hoja de datos )
| Número de pieza | MC10E212 | |
| Descripción | 3-BIT SCANNABLE REGISTERED ADDRESS DRIVER | |
| Fabricantes | ON Semiconductor | |
| Logotipo |  |
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MC10E212, MC100E212
5V ECL 3-Bit Scannable
Registered Address Driver
The MC10E/100E212 is a scannable registered ECL driver typically
used as a fan-out memory address driver for ECL cache driving. In a
VLSI array based CPU design, use of the E212 allows the user to
conserve array output cell functionality and also output pins.
The input shift register is designed with control logic which greatly
facilitates its use in boundary scan applications.
The 100 Series contains temperature compensation.
• Scannable Version E112 Driver
• 1025 ps Max. CLK to Output
• Dual Differential Outputs
• Master Reset
• PECL Mode Operating Range: VCC= 4.2 V to 5.7 V
with VEE= 0 V
• NECL Mode Operating Range: VCC= 0 V
with VEE= −4.2 V to −5.7 V
• Internal Input Pulldown Resistors
• ESD Protection: > 1 KV HBM, > 75 V MM
• Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
• Moisture Sensitivity Level 1
For Additional Information, see Application Note AND8003/D
• Flammability Rating: UL−94 code V−0 @ 1/8”,
Oxygen Index 28 to 34
• Transistor Count = 259 devices
http://onsemi.com
MARKING
DIAGRAMS
1 28
PLCC−28
FN SUFFIX
CASE 776
A = Assembly Location
WL = Wafer Lot
YY = Year
WW = Work Week
MC10E212FN
AWLYYWW
1 28
MC100E212FN
AWLYYWW
ORDERING INFORMATION
Device
Package
Shipping
MC10E212FN
PLCC−28 37 Units/Rail
MC10E212FNR2 PLCC−28 500 Units/Reel
MC100E212FN
PLCC−28 37 Units/Rail
MC100E212FNR2 PLCC−28 500 Units/Reel
© Semiconductor Components Industries, LLC, 2006
June, 2006 − Rev. 5
1
Publication Order Number:
MC10E212/D
1 page  
MC10E212, MC100E212
2. Within-gate skew is defined as the difference in delays between various outputs of a gate when driven from the same input.
Driver
Device
Q
Q
50 W
D
Receiver
Device
D
50 W
V TT
VTT = VCC − 2.0 V
Figure 1. Typical Termination for Output Driver and Device Evaluation
(See Application Note AND8020 − Termination of ECL Logic Devices.)
Resource Reference of Application Notes
AN1404
− ECLinPS Circuit Performance at Non−Standard VIH Levels
AN1405
− ECL Clock Distribution Techniques
AN1406
− Designing with PECL (ECL at +5.0 V)
AN1503
− ECLinPS I/O SPICE Modeling Kit
AN1504
− Metastability and the ECLinPS Family
AN1568
− Interfacing Between LVDS and ECL
AN1596
− ECLinPS Lite Translator ELT Family SPICE I/O Model Kit
AN1650
− Using Wire−OR Ties in ECLinPS Designs
AN1672
− The ECL Translator Guide
AND8001 − Odd Number Counters Design
AND8002 − Marking and Date Codes
AND8020 − Termination of ECL Logic Devices
http://onsemi.com
5
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| Páginas | Total 7 Páginas | |
| PDF Descargar | [ Datasheet MC10E212.PDF ] | |
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