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PDF MC10E160 Data sheet ( Hoja de datos )
| Número de pieza | MC10E160 | |
| Descripción | 12-BIT PARITY GENERATOR/CHECKER | |
| Fabricantes | ON Semiconductor | |
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MC10E160, MC100E160
5V ECL 12-Bit Parity
Generator/Checker
The MC10E/100E160 is a 12-bit parity generator/checker. The Q
output is HIGH when an odd number of inputs are HIGH. A HIGH on
the Enable input (EN) forces the Q output LOW.
The 100 Series contains temperature compensation.
• Provides Odd-HIGH Parity of 12 Inputs
• Shiftable Output Register with Hold
• 900 ps Max. D to Q/Q Output
• Enable
• Asynchronous Register Reset
• Dual Clocks
• PECL Mode Operating Range: VCC = 4.2 V to 5.7 V
with VEE = 0 V
• NECL Mode Operating Range: VCC = 0 V
with VEE = −4.2 V to −5.7 V
• Internal Input to 50 KW Pulldown Resistors
• ESD Protection: Human Body Model; > 1 KV,
Machine Model; > 7 V
• Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
• Moisture Sensitivity Level 1
For Additional Information, see Application Note AND8003/D
• Flammability Rating: UL 94 V−0 @ 0.125 in,
Oxygen Index: 28 to 34
• Transistor Count = 312 devices
http://onsemi.com
MARKING
DIAGRAMS
1 28
PLCC−28
FN SUFFIX
CASE 776
A = Assembly Location
WL = Wafer Lot
YY = Year
WW = Work Week
MC10E160FN
AWLYYWW
1 28
MC100E160FN
AWLYYWW
ORDERING INFORMATION
Device
Package
Shipping†
MC10E160FN
PLCC−28 37 Units/Rail
MC10E160FNR2 PLCC−28 500 Units/Reel
MC100E160FN
PLCC−28 37 Units/Rail
MC100E160FNR2 PLCC−28 500 Units/Reel
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
© Semiconductor Components Industries, LLC, 2006
June, 2006 − Rev. 6
1
Publication Order Number:
MC10E160/D
1 page  
MC10E160, MC100E160
AC CHARACTERISTICS VCCx= 5.0 V; VEE= 0.0 V or VCCx= 0.0 V; VEE= −5.0 V (Note 10)
0°C 25°C
85°C
Symbol
Characteristic
Min Typ Max Min Typ Max Min Typ Max Unit
fMAX
tPLH
tPHL
Maximum Toggle Frequency
Propagation Delay to Output
D to Q
En to Q
700
400
300
1100
650
550
950
750
700 1100
400 650 950
300 550 750
700 1100
MHz
ps
400 650 950
300 550 750
CLK to Y 275 500 700 275 500 700 275 500 700
R to Y 275 500 725 275 500 725 275 500 725
ts Setup Time
D 1200 900
1200 900
1200 900
ps
HOLD 600 300
600 300
600 300
S-IN 350 150
350 150
350 150
SHIFT 500 250
500 250
500 250
th Hold Time
D − 400 − 900
− 400 − 900
− 400 − 900
ps
HOLD 100 − 300
100 − 300
100 − 300
S-IN 300 −150
300 −150
300 −150
SHIFT 200 − 250
200 − 250
200 − 250
tJITTER
tr
tf
Random Clock Jitter (RMS)
Rise/Fall Time
(20 - 80%)
<1 <1 <1
300 450 650 300 450 650 300 450 650
ps
ps
NOTE: Devices are designed to meet the AC specifications shown in the above table, after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 LFPM is maintained.
10. 10 Series: VEE can vary −0.46 V / +0.06 V.
100 Series: VEE can vary −0.46 V / +0.8 V.
http://onsemi.com
5
5 Page | ||
| Páginas | Total 8 Páginas | |
| PDF Descargar | [ Datasheet MC10E160.PDF ] | |
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