|
|
PDF MC100LVEL14 Data sheet ( Hoja de datos )
| Número de pieza | MC100LVEL14 | |
| Descripción | 1:5 Clock Distribution Chip | |
| Fabricantes | ON Semiconductor | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de MC100LVEL14 (archivo pdf) en la parte inferior de esta página. Total 7 Páginas | ||
|
No Preview Available !
MC100LVEL14
3.3 V ECL 1:5 Clock
Distribution Chip
Description
The MC100LVEL14 is a low skew 1:5 clock distribution chip
designed explicitly for low skew clock distribution applications. The
device can be driven by either a differential or single-ended ECL or, if
positive power supplies are used, PECL input signal. The LVEL14 is
functionally and pin compatible with the EL14 but is designed to
operate in ECL or PECL mode for a voltage supply range of −3.0 V to
−3.8 V ( or 3.0 V to 3.8 V).
The LVEL14 features a multiplexed clock input to allow for the
distribution of a lower speed scan or test clock along with the high speed
system clock. When LOW (or left open and pulled LOW by the input
pulldown resistor) the SEL pin will select the differential clock input.
The common enable (EN) is synchronous so that the outputs will only
be enabled/disabled when they are already in the LOW state. This
avoids any chance of generating a runt clock pulse when the device is
enabled/disabled as can happen with an asynchronous control. The
internal flip flop is clocked on the falling edge of the input clock,
therefore all associated specification limits are referenced to the
negative edge of the clock input.
The VBB pin, an internally generated voltage supply, is available to
this device only. For single-ended input conditions, the unused
differential input is connected to VBB as a switching reference voltage.
VBB may also rebias AC coupled inputs. When used, decouple VBB and
VCC via a 0.01 mF capacitor and limit current sourcing or sinking to 0.5
mA. When not used, VBB should be left open.
Features
• 50 ps Output-to-Output Skew
• Synchronous Enable/Disable
• Multiplexed Clock Input
• ESD Protection: Human Body Model > 2 kV
• The 100 Series Contains Temperature Compensation
• PECL Mode Operating Range:
VCC = 3.0 V to 3.8 V with VEE = 0 V
• NECL Mode Operating Range:
VCC = 0 V with VEE = −3.0 V to −3.8 V
• Internal Input Pulldown Resistors on CLK
• Q Output will Default LOW with Inputs Open or at VEE
• Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
• Moisture Sensitivity: Level 3 (Pb-Free)
• Flammability Rating: UL 94 V−0 @ 0.125 in,
Oxygen Index: 28 to 34
• Transistor Count = 303 Devices
• These Devices are Pb-Free, Halogen Free and are RoHS Compliant
www.onsemi.com
20
1
SOIC−20 WB
DW SUFFIX
CASE 751D−05
MARKING DIAGRAM
20
100LVEL14
AWLYYWWG
1
A = Assembly Location
WL = Wafer Lot
YY = Year
WW = Work Week
G = Pb-Free Package
ORDERING INFORMATION
Device
Package Shipping†
MC100LVEL14DWG
SOIC−20 WB 38 Units / Tube
(Pb-Free)
MC100LVEL14DWR2G SOIC−20 WB 1000 Tape & Reel
(Pb-Free)
†For information on tape and reel specifications, in-
cluding part orientation and tape sizes, please refer
to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
© Semiconductor Components Industries, LLC, 2016
July, 2016 − Rev. 10
1
Publication Order Number:
MC100LVEL14/D
1 page  
MC100LVEL14
Driver
Device
Q
Q
Zo = 50 W
Zo = 50 W
50 W
50 W
D
Receiver
Device
D
VTT
VTT = VCC − 2.0 V
Figure 3. Typical Termination for Output Driver and Device Evaluation
(See Application Note AND8020/D − Termination of ECL Logic Devices)
Resource Reference of Application Notes
AN1405/D − ECL Clock Distribution Techniques
AN1406/D − Designing with PECL (ECL at +5.0 V)
AN1503/D − ECLinPSt I/O SPiCE Modeling Kit
AN1504/D − Metastability and the ECLinPS Family
AN1568/D − Interfacing Between LVDS and ECL
AN1672/D − The ECL Translator Guide
AND8001/D − Odd Number Counters Design
AND8002/D − Marking and Date Codes
AND8020/D − Termination of ECL Logic Devices
AND8066/D − Interfacing with ECLinPS
AND8090/D − AC Characteristics of ECL Devices
www.onsemi.com
5
5 Page | ||
| Páginas | Total 7 Páginas | |
| PDF Descargar | [ Datasheet MC100LVEL14.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| MC100LVEL11 | Low Voltage 1:2 Differential Fanout Buffer |  Motorola Semiconductors |
| MC100LVEL11 | Low Voltage 1:2 Differential Fanout Buffer | ON Semiconductor |
| MC100LVEL12 | Low Impedance Driver | Motorola Semiconductors |
| MC100LVEL12 | Low Impedance Driver | ON Semiconductor |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |