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PDF MC100LVEL11 Data sheet ( Hoja de datos )
| Número de pieza | MC100LVEL11 | |
| Descripción | Low Voltage 1:2 Differential Fanout Buffer | |
| Fabricantes | ON Semiconductor | |
| Logotipo |  |
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MC100LVEL11
3.3V ECL 1:2
Differential Fanout Buffer
Description
The MC100LVEL11 is a differential 1:2 fanout buffer. The device is
functionally similar to the E111 device but with higher performance
capabilities. Having within-device skews and output transition times
significantly improved over the E111, the LVEL11 is ideally suited for
those applications which require the ultimate in AC performance.
The differential inputs of the LVEL11 employ clamping circuitry to
maintain stability under open input conditions. If the inputs are left
open (pulled to VEE) the Q outputs will go LOW.
Features
• 330 ps Propagation Delay
• 5 ps Skew Between Outputs
• High Bandwidth Output Transitions
• The 100 Series Contains Temperature Compensation
• PECL Mode Operating Range: VCC = 3.0 V to 3.8 V
with VEE = 0 V
• NECL Mode Operating Range: VCC = 0 V
with VEE = −3.0 V to −3.8 V
• Internal Input Pulldown Resistors on D,
Pullup and Pulldown Resistors on D
• Q Output will Default LOW with Inputs Open or at VEE
• These Devices are Pb−Free and are RoHS Compliant
Q0 1
Q0 2
8 VCC
7D
Q1 3
6D
Q1 4
5 VEE
Figure 1. Logic Diagram and Pinout Assignment
www.onsemi.com
8
1
SOIC−8
D SUFFIX
CASE 751
8
1
TSSOP−8
DT SUFFIX
CASE 948R
MARKING
DIAGRAMS*
8
KVL11
ALYW
G
1
8
KV11
ALYWG
G
1
1
DFN8
MN SUFFIX
CASE 506AA
1
3ZMG
G
A = Assembly Location
L = Wafer Lot
Y = Year
W = Work Week
M = Date Code
G = Pb−Free Package
(Note: Microdot may be in either location)
*For additional marking information, refer to
Application Note AND8002/D.
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 5 of this data sheet.
© Semiconductor Components Industries, LLC, 2015
January, 2015 − Rev. 13
1
Publication Order Number:
MC100LVEL11/D
1 page  
MC100LVEL11
ORDERING INFORMATION
Device
Package
Shipping†
MC100LVEL11DG
SOIC−8
(Pb−Free)
98 Units / Rail
MC100LVEL11DR2G
SOIC−8
(Pb−Free)
2500 / Tape & Reel
MC100LVEL11DTG
TSSOP−8
(Pb−Free)
100 Units / Rail
MC100LVEL11DTR2G
TSSOP−8
(Pb−Free)
2500 / Tape & Reel
MC100LVEL11MNR4G
DFN8
(Pb−Free)
1000 / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
Resource Reference of Application Notes
AN1405/D − ECL Clock Distribution Techniques
AN1406/D − Designing with PECL (ECL at +5.0 V)
AN1503/D − ECLinPSt I/O SPiCE Modeling Kit
AN1504/D − Metastability and the ECLinPS Family
AN1568/D − Interfacing Between LVDS and ECL
AN1672/D − The ECL Translator Guide
AND8001/D − Odd Number Counters Design
AND8002/D − Marking and Date Codes
AND8020/D − Termination of ECL Logic Devices
AND8066/D − Interfacing with ECLinPS
AND8090/D − AC Characteristics of ECL Devices
www.onsemi.com
5
5 Page | ||
| Páginas | Total 8 Páginas | |
| PDF Descargar | [ Datasheet MC100LVEL11.PDF ] | |
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