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PDF MC100H642 Data sheet ( Hoja de datos )

Número de pieza MC100H642
Descripción 68030/040 PECL-TTL CLOCK DRIVER
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MC10H642, MC100H642
68030/040 PECL to TTL
Clock Driver
Description
The MC10H/100H642 generates the necessary clocks for the
68030, 68040 and similar microprocessors. It is guaranteed to meet the
clock specifications required by the 68030 and 68040 in terms of
parttopart skew, withinpart skew and also duty cycle skew.
The user has a choice of using either TTL or PECL (ECL referenced
to +5.0 V) for the input clock. TTL clocks are typically used in present
MPU systems. However, as clock speeds increase to 50 MHz and
beyond, the inherent superiority of ECL (particularly differential
ECL) as a means of clock signal distribution becomes increasingly
evident. The H642 also uses differential PECL internally to achieve its
superior skew characteristic.
The H642 includes dividebytwo and dividebyfour stages, both
to achieve the necessary duty cycle skew and to generate MPU clocks
as required. A typical 50 MHz processor application would use an
input clock running at 100 MHz, thus obtaining output clocks at
50 MHz and 25 MHz (see Logic Diagram).
The 10H version is compatible with MECL 10HECL logic levels,
while the 100H version is compatible with 100K levels (referenced to
+5.0 V).
Features
Generates Clocks for 68030/040
Meets 030/040 Skew Requirements
TTL or PECL Input Clock
Extra TTL and PECL Power/Ground Pins
Asynchronous Reset
Single +5.0 V Supply
PbFree Packages are Available*
Function
Reset(R): LOW on RESET forces all Q outputs LOW.
Select(SEL): LOW selects the ECL input source (DE/DE). HIGH
selects the TTL input source (DT).
The H642 also contains circuitry to force a stable input state of the
ECL differential input pair, should both sides be left open. In this Case,
the DE side of the input is pulled LOW, and DE goes HIGH.
Power Up: The device is designed to have positive edges of the ÷2
and ÷4 outputs synchronized at Power Up.
http://onsemi.com
PLCC28
FN SUFFIX
CASE 776
MARKING DIAGRAM*
1
MCxxxH642G
AWLYYWW
xxx = 10 or 100
A = Assembly Location
WL = Wafer Lot
YY = Year
WW = Work Week
G = PbFree Package
*For additional marking information, refer to
Application Note AND8002/D.
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 8 of this data sheet.
*For additional information on our PbFree strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
© Semiconductor Components Industries, LLC, 2006
November, 2006 Rev. 8
1
Publication Order Number:
MC10H642/D

1 page




MC100H642 pdf
MC10H642, MC100H642
10/100H642 DUTY CYCLE CONTROL
To maintain a duty cycle of ±5% at 50 MHz, limit the load capacitance and/or power supply variation as shown in Figures
1 and 2. For a ±2.5% duty cycle limit, see Figures 3 and 4. Figures 5 and 6 show duty cycle variation with temperature.
Figure 7 shows typical TPD versus load. Figure 8 shows reset recovery time. Figure 9 shows output states after power up.
Best duty cycle control is obtained with a single mP load and minimum line length.
11
11
10 4.75
5.00 10
5.25
4.75
5.00
5.25
9
0 10 20 30 40 50 60
CAPACITIVE LOAD (pF)
Figure 3. MC10H642 Positive PW versus Load
@ ±5% VCC, TA = 25°C
10.6
10.4
10.2
10.0 4.875
5.00
9.8
5.125
9.6
9.4
9.2 0
10 20 30 40 50
CAPACITIVE LOAD (pF)
60
Figure 5. MC10H642 Positive PW versus Load
@ ±2.5% VCC, TA = 25°C
10.4
10.2
10.0
0 pF
9.8 25 pF
50 pF
9.6
9.4
0 20 40 60 80 100
TEMPERATURE (°C)
Figure 7. MC10H642 Positive PW versus Temperature,
VCC = 5.0 V
9
0 10 20 30 40 50 60
CAPACITIVE LOAD (pF)
Figure 4. MC10H642 Negative PW versus Load
@ ±5% VCC, TA = 25°C
10.8
10.6
10.4
10.2 4.875
5.00
10.0
5.125
9.8
9.6
9.4
0 10 CAPAC2I0TIVE LO3A0D (pF) 40 50 60
Figure 6. MC10H642 Negative PW versus Load
@ ±2.5% VCC, TA = 25°C
10.5
10.3
10.1
0 pF
9.9 25 pF
50 pF
9.7
9.5
0 20 40 60 80 100
TEMPERATURE (°C)
Figure 8. MC10H642 Negative PW versus
Temperature, VCC = 5.0 V
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