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PDF MC100EPT25 Data sheet ( Hoja de datos )
| Número de pieza | MC100EPT25 | |
| Descripción | Differential LVECL/ECL to LVTTL Translator | |
| Fabricantes | ON Semiconductor | |
| Logotipo |  |
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MC100EPT25
-3.3 V / -5 V Differential
ECL to +3.3 V LVTTL
Translator
Description
The MC100EPT25 is a Differential ECL to LVTTL translator. This
device requires +3.3 V, −3.3 V to −5.2 V, and ground. The small
outline 8-lead package and the single gate of the EPT25 make it ideal
for applications which require the translation of a clock or data signal.
The VBB output allows the EPT25 to also be used in a single-ended
input mode. In this mode the VBB output is tied to the D input for
a inverting buffer or the D input for a non-inverting buffer. If used, the
VBB pin should be bypassed to ground with at least a 0.01 mF
capacitor.
Features
• 1.1 ns Typical Propagation Delay
• Maximum Frequency > 275 MHz Typical
• Operating Range:
♦ VCC = 3.0 V to 3.6 V; VEE = −5.5 V to −3.0 V; GND = 0 V
• 24 mA TTL Outputs
• Q Output Will Default LOW with Inputs Open or at VEE
• VBB Output
• Open Input Default State
• Safety Clamp on Inputs
• These Devices are Pb-Free, Halogen Free and are RoHS Compliant
www.onsemi.com
8
1
SOIC−8 NB
D SUFFIX
CASE
751−07
8
1
TSSOP−8
DT SUFFIX
CASE
948R−02
DFN−8
MN SUFFIX
CASE 506AA
MARKING DIAGRAMS*
8
KPT25
ALYW
G
1
8
KA25
ALYWG
G
1
14
A = Assembly Location
L = Wafer Lot
Y = Year
W = Work Week
M = Date Code
G = Pb-Free Package
(Note: Microdot may be in either location)
*For additional marking information, refer to
Application Note AND8002/D.
© Semiconductor Components Industries, LLC, 2016
August, 2016 − Rev. 17
ORDERING INFORMATION
Device
MC100EPT25DG
MC100EPT25DR2G
MC100EPT25DTG
MC100EPT25DTR2G
MC100EPT25MNR4G
Package
SOIC−8 NB
(Pb-Free)
SOIC−8 NB
(Pb-Free)
TSSOP−8
(Pb-Free)
TSSOP−8
(Pb-Free)
DFN−8
(Pb-Free)
Shipping†
98 Units/Tube
2500/Tape & Reel
100 Units/Tube
2500/Tape & Reel
1000/Tape & Reel
†For information on tape and reel specifications, in-
cluding part orientation and tape sizes, please refer
to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
1 Publication Order Number:
MC100EPT25/D
1 page  
MC100EPT25
APPLICATION
TTL RECEIVER
CHARACTERISTIC TEST
*CL includes
fixture
capacitance
CL*
RL
AC TEST LOAD
GND
Figure 3. TTL Output Loading Used for Device Evaluation
Resource Reference of Application Notes
AN1405/D − ECL Clock Distribution Techniques
AN1406/D − Designing with PECL (ECL at +5.0 V)
AN1503/D − ECLinPSt I/O SPiCE Modeling Kit
AN1504/D − Metastability and the ECLinPS Family
AN1568/D − Interfacing Between LVDS and ECL
AN1672/D − The ECL Translator Guide
AND8001/D − Odd Number Counters Design
AND8002/D − Marking and Date Codes
AND8020/D − Termination of ECL Logic Devices
AND8066/D − Interfacing with ECLinPS
AND8090/D − AC Characteristics of ECL Devices
www.onsemi.com
5
5 Page | ||
| Páginas | Total 8 Páginas | |
| PDF Descargar | [ Datasheet MC100EPT25.PDF ] | |
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