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PDF MC100EP139 Data sheet ( Hoja de datos )
| Número de pieza | MC100EP139 | |
| Descripción | Clock Generation Chip | |
| Fabricantes | ON Semiconductor | |
| Logotipo |  |
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MC10EP139, MC100EP139
3.3 V / 5 V ECL ÷2/4, ÷4/5/6
Clock Generation Chip
Description
The MC10/100EP139 is a low skew ÷2/4, ÷4/5/6 clock generation chip
designed explicitly for low skew clock generation applications. The
internal dividers are synchronous to each other, therefore, the common
output edges are all precisely aligned.
The common enable (EN) is synchronous so that the internal dividers
will only be enabled/disabled when the internal clock is already in the
LOW state. This avoids any chance of generating a runt clock pulse on
the internal clock when the device is enabled/disabled as can happen with
an asynchronous control. The internal enable flip-flop is clocked on the
falling edge of the input clock, therefore, all associated specification
limits are referenced to the negative edge of the clock input.
Upon start-up, the internal flip-flops will attain a random state;
therefore the master reset (MR) input may require assertion to ensure
system synchronization. Internal divider design ensures synchronization
between the ÷2/4 and the ÷4/5/6 outputs within a device. All VCC and
VEE pins must be externally connected to power supply to guarantee
proper operation.
The VBB Pin, an internally generated voltage supply, is available to this
device only. For Single-Ended input conditions, the unused differential
input is connected to VBB as a switching reference voltage. VBB may also
rebias AC coupled inputs. When used, decouple VBB and VCC via a
0.01 mF capacitor and limit current sourcing or sinking to 0.5 mA. When
not used, VBB should be left open.
The 100 Series contains temperature compensation.
Features
• Maximum Frequency = > 1.0 GHz Typical
• 50 ps Output-to-Output Skew
• PECL Mode Operating Range:
VCC = 3.0 V to 5.5 V with VEE = 0 V
• NECL Mode Operating Range:
VCC = 0 V with VEE = −3.0 V to −5.5 V
• Open Input Default State
• Safety Clamp on Inputs
• Synchronous Enable/Disable
• Master Reset for Synchronization of Multiple Chips
• VBB Output
• These Devices are Pb-Free, Halogen Free and are RoHS Compliant
www.onsemi.com
11
TSSOP−20 WB
DT SUFFIX
CASE 948E
SOIC−20 WB
DW SUFFIX
CASE 751D
QFN−20
MN SUFFIX
CASE 485E
MARKING DIAGRAMS*
HEP or KEP
139
ALYWG
G
20
MCXXXEP139
AWLYYWWG
1
TSSOP−20 WB SOIC−20 WB
20
1 XXXX
EP139
ALYWG
G
QFN−20
HEP = MC10EP
KEP = MC100EP
XXX = 10 or 100
A = Assembly Location
L,WL = Wafer Lot
Y, YY = Year
W, WW = Work Week
G or G = Pb-Free Package
(Note: Microdot may be in either location)
*For additional marking information, refer to
Application Note AND8002/D.
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 11 of this data sheet.
© Semiconductor Components Industries, LLC, 2016
August, 2016 − Rev. 14
1
Publication Order Number:
MC10EP139/D
1 page  
MC10EP139, MC100EP139
Table 5. 10EP DC CHARACTERISTICS, PECL (VCC = 3.3 V, VEE = 0 V (Note 1))
−40°C
25°C
85°C
Symbol
Characteristic
Min Typ Max Min Typ Max Min Typ Max Unit
IEE
VOH
VOL
VIH
VIL
VBB
VIHCMR
Power Supply Current
Output HIGH Voltage (Note 2)
Output LOW Voltage (Note 2)
Input HIGH Voltage (Single-Ended)
Input LOW Voltage (Single-Ended)
Output Voltage Reference
Input HIGH Voltage Common Mode
Range (Differential Configuration)
(Note 3)
65
2165
1365
2090
1365
1790
2.0
82
2290
1490
1890
105
2415
1615
2415
1690
1990
3.3
65
2230
1430
2155
1460
1855
2.0
83
2355
1555
1955
105
2480
1680
2480
1755
2055
3.3
65
2290
1490
2215
1490
1915
2.0
84
2415
1615
2015
105
2540
1740
2540
1815
2115
3.3
mA
mV
mV
mV
mV
mV
V
IIH Input HIGH Current
150 150 150 mA
IIL Input LOW Current
0.5 0.5 0.5 mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
1. Input and output parameters vary 1:1 with VCC. VEE can vary +0.3 V to −2.2 V.
2. All loading with 50 W to VCC − 2.0 V (see Figure 10).
3. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential
input signal.
Table 6. 10EP DC CHARACTERISTICS, PECL (VCC = 5.0 V, VEE = 0 V (Note 1))
−40°C
25°C
85°C
Symbol
Characteristic
Min Typ Max Min Typ Max Min Typ Max Unit
IEE
VOH
VOL
VIH
VIL
VBB
VIHCMR
Power Supply Current
Output HIGH Voltage (Note 2)
Output LOW Voltage (Note 2)
Input HIGH Voltage (Single-Ended)
Input LOW Voltage (Single-Ended)
Output Voltage Reference
Input HIGH Voltage Common Mode
Range (Differential Configuration)
(Note 3)
65
3865
3065
3790
3065
3490
2.0
82
3990
3190
3590
105
4115
3315
4115
3390
3690
5.0
65
3930
3130
3855
3130
3555
2.0
83
4055
3255
3655
105
4180
3380
4180
3455
3755
5.0
65
3990
3190
3915
3190
3615
2.0
84
4115
3315
3715
105
4240
3440
4240
3515
3815
5.0
mA
mV
mV
mV
mV
mV
V
IIH Input HIGH Current
150 150 150 mA
IIL Input LOW Current
0.5 0.5 0.5 mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
1. Input and output parameters vary 1:1 with VCC. VEE can vary +2.0 V to −0.5 V.
2. All loading with 50 W to VCC − 2.0 V (see Figure 10).
3. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential
input signal.
www.onsemi.com
5
5 Page 
MC10EP139, MC100EP139
ORDERING INFORMATION
Device
Package
Shipping†
MC10EP139DTG
TSSOP−20 WB
(Pb-Free)
75 Units / Tube
MC10EP139DTR2G
TSSOP−20 WB
(Pb-Free)
2500 / Tape & Reel
MC10EP139DWG
SOIC−20 WB
(Pb-Free)
38 Units / Tube
MC10EP139DWR2G
SOIC−20 WB
(Pb-Free)
1000 / Tape & Reel
MC100EP139DTG
TSSOP−20 WB
(Pb-Free)
75 Units / Tube
MC100EP139DTR2G
TSSOP−20 WB
(Pb-Free)
2500 / Tape & Reel
MC100EP139DWG
SOIC−20 WB
(Pb-Free)
38 Units / Tube
MC100EP139DWR2G
SOIC−20 WB
(Pb-Free)
1000 / Tape & Reel
MC100EP139MNG
QFN−20
(Pb-Free)
92 Units / Tube
MC100EP139MNTXG
QFN−20
(Pb-Free)
3000 / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
Resource Reference of Application Notes
AN1405/D − ECL Clock Distribution Techniques
AN1406/D − Designing with PECL (ECL at +5.0 V)
AN1503/D − ECLinPSt I/O SPiCE Modeling Kit
AN1504/D − Metastability and the ECLinPS Family
AN1568/D − Interfacing Between LVDS and ECL
AN1672/D − The ECL Translator Guide
AND8001/D − Odd Number Counters Design
AND8002/D − Marking and Date Codes
AND8020/D − Termination of ECL Logic Devices
AND8066/D − Interfacing with ECLinPS
AND8090/D − AC Characteristics of ECL Devices
www.onsemi.com
11
11 Page | ||
| Páginas | Total 14 Páginas | |
| PDF Descargar | [ Datasheet MC100EP139.PDF ] | |
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