PDF MC100EL56 Data sheet ( Hoja de datos )

Número de pieza	MC100EL56
Descripción	Dual Differential 2:1 Multiplexer
Fabricantes	ON Semiconductor
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No Preview Available ! MC100EL56 5 V ECL Dual Differential 2:1 Multiplexer Description The MC100EL56 is a dual, fully differential 2:1 multiplexer. The differential data path makes the device ideal for multiplexing low skew clock or other skew sensitive signals. Multiple VBB pins are provided to ease AC coupling input signals. The VBB pins, an internally generated voltage supply, are available to this device only. For single-ended input conditions, the unused differential input is connected to VBB as a switching reference voltage. VBB may also rebias AC coupled inputs. When used, decouple VBB and VCC via a 0.01 mF capacitor and limit current sourcing or sinking to 0.5 mA. When not used, VBB should be left open. The device features both individual and common select inputs to address both data path and random logic applications. The differential inputs have special circuitry which ensures device stability under open input conditions. When both differential inputs are left open, the D input will pull down to VEE. The D input will bias around VCC/2 forcing the Q output LOW. Features • 580 ps Typical Propagation Delays • Separate and Common Select • The 100 Series Contains Temperature Compensation • PECL Mode Operating Range: ♦ VCC = 4.2 V to 5.7 V with VEE = 0 V • NECL Mode Operating Range: ♦ VCC = 0 V with VEE = −4.2 V to −5.7 V • Internal Input Pulldown Resistors on D(s), SEL(s), and COM_SEL • Q Output will Default LOW with Inputs Open or at VEE • These Devices are Pb-Free, Halogen Free and are RoHS Compliant www.onsemi.com SOIC−20 WB DW SUFFIX CASE 751D−05 MARKING DIAGRAM* 20 100EL56 AWLYYWWG 1 A = Assembly Location WL = Wafer Lot YY = Year WW = Work Week G = Pb-Free Package *For additional marking information, refer to Application Note AND8002/D. ORDERING INFORMATION Device MC100EL56DWG MC100EL56DWR2G Package Shipping† SOIC−20 WB (Pb-Free) 38 Units/Tube SOIC−20 wB 1000/Tape & Reel (Pb-Free) †For information on tape and reel specifications, in- cluding part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. © Semiconductor Components Industries, LLC, 2016 July, 2016 − Rev. 9 1 Publication Order Number: MC100EL56/D 1 page MC100EL56 Driver Device Q Q Zo = 50 W Zo = 50 W 50 W 50 W D Receiver Device D VTT VTT = VCC − 2.0 V Figure 2. Typical Termination for Output Driver and Device Evaluation (See Application Note AND8020/D − Termination of ECL Logic Devices.) Resource Reference of Application Notes AN1405/D − ECL Clock Distribution Techniques AN1406/D − Designing with PECL (ECL at +5.0 V) AN1503/D − ECLinPSt I/O SPiCE Modeling Kit AN1504/D − Metastability and the ECLinPS Family AN1568/D − Interfacing Between LVDS and ECL AN1672/D − The ECL Translator Guide AND8001/D − Odd Number Counters Design AND8002/D − Marking and Date Codes AND8020/D − Termination of ECL Logic Devices AND8066/D − Interfacing with ECLinPS AND8090/D − AC Characteristics of ECL Devices www.onsemi.com 5 5 Page

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