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MC-4R256FKK8K Schematic ( PDF Datasheet ) - Elpida Memory

Teilenummer MC-4R256FKK8K
Beschreibung 256MB 32-bit Direct Rambus DRAM RIMM Module
Hersteller Elpida Memory
Logo Elpida Memory Logo 




Gesamt 13 Seiten
MC-4R256FKK8K Datasheet, Funktion
PRELIMINARY DATA SHEET
256MB 32-bit Direct Rambus DRAM RIMMModule
MC-4R256FKK8K (64M words × 18 bits × 2 channels)
Description
The 32-bit Direct Rambus RIMM module is a general-
purpose high-performance lines of memory modules
suitable for use in a broad range of applications
including computer memory, personal computers,
workstations, and other applications where high
bandwidth and latency are required.
The 32-bit RIMM module consists of 288Mb Direct
Rambus DRAM (Direct RDRAM) devices. These are
extremely high-speed CMOS DRAMs organized as
16M words by 18 bits. The use of Rambus Signaling
Level (RSL) technology permits the use of conventional
system and board design technologies. The 32-bit
RIMM modules support 800MHz transfer rate per pin,
resulting in total module bandwidth of 3.2GB/s.
Features
256MB Direct RDRAM storage and 256 banks total
on module
2 independent Direct RDRAM channels, 1 pass
through and 1 terminated on 32-bit RIMM module
High speed 800MHz Direct RDRAM devices
232 edge connector pads with 1mm pad spacing
Module PCB size: 133.35mm × 39.925mm ×
1.27mm
Gold plated edge connector pads contacts
Serial Presence Detect (SPD) support
Operates from a 2.5V (±5%) supply
Low power and power down self refresh modes
Separate Row and Column buses for higher
efficiency
The 32-bit RIMM module provides two independent 18
bit memory channels to facilitate compact system
design. The "Thru" Channel enters and exits the
module to support a connection to or from a controller,
memory slot, or termination. The "Term" Channel is
terminated on the module and supports a connection
from a controller or another memory slot.
The RDRAMarchitecture enables the highest
sustained bandwidth for multiple, simultaneous,
randomly addressed memory transactions. The
separate control and data buses with independent row
and column control yield over 95% bus efficiency. The
RDRAM device multi-bank architecture supports up to
four simultaneous transactions per device.
Document No. E0253N10 (Ver. 1.0)
Date Published April 2002 (K) Japan
URL: http://www.elpida.com
Elpida Memory, Inc. 2002
Elpida Memory, Inc. is a joint venture DRAM company of NEC Corporation and Hitachi, Ltd.






MC-4R256FKK8K Datasheet, Funktion
Signal
GND
SA0
SA1
SA2
SCL
SDA
SVDD
SWP
VCMOS
VDD
VREF
Module
connector pads
I/O
A1, A3, A5, A7, A9, A11, A13, A15,
A17, A19, A21, A23, A25, A27, A29,
A31, A33, A35, A37, A39, A41, A43,
A45, A47, A49, A51, A53, A55, A57,
A59, A62, A64, A66, A68, A70, A72,
A74, A84, A86, A88, A90, A92, A94,
A96, A98, A100, A102, A104, A106,
A108, A110, A112, A114, A116, B1,
B3, B5, B7, B9, B11, B13, B15, B17,
B19, B21, B23, B25, B27, B29, B31,
B33, B35, B37, B39, B41, B43, B45,
B47, B49, B51, B53, B55, B57, B59,
B62, B64, B66, B68, B70, B72, B74,
B84, B86, B88, B90, B92, B94, B96,
B98, B100, B102, B104, B106,
B108, B110, B112, B114, B116
A81 I
B81 I
A83 I
A79 I
B79 I/O
A77
B77 I
B75
A69, B69, A76, B76, A78, B78, A80,
B80, A82, B82
A75
MC-4R256FKK8K
Type
Description
Ground reference for RDRAM core and
interface.
SVDD
SVDD
SVDD
SVDD
SVDD
SVDD
Serial Presence Detect Address 0
Serial Presence Detect Address 1.
Serial Presence Detect Address 2.
Serial Presence Detect Clock.
Serial Presence Detect Data (Open Collector
I/O).
SPD Voltage. Used for signals SCL, SDA,
SWE, SA0, SA1 and SA2.
Serial Presence Detect Write Protect (active
high). When low, the SPD can be written as
well as read.
CMOS I/O Voltage. Used for signals CMD,
SCK, SIN, SOUT.
Supply voltage for the RDRAM core and
interface logic.
Logic threshold reference voltage for both
"Thru" Channel and "Term" Channel RSL
signals.
Preliminary Data Sheet E0253N10 (Ver. 1.0)
6

6 Page









MC-4R256FKK8K pdf, datenblatt
MC-4R256FKK8K
CAUTION FOR HANDLING MEMORY MODULES
When handling or inserting memory modules, be sure not to touch any components on the modules, such as
the memory ICs, chip capacitors and chip resistors. It is necessary to avoid undue mechanical stress on
these components to prevent damaging them.
In particular, do not push module cover or drop the modules in order to protect from mechanical defects,
which would be electrical defects.
When re-packing memory modules, be sure the modules are not touching each other.
Modules in contact with other modules may cause excessive mechanical stress, which may damage the
modules.
MDE0202
NOTES FOR CMOS DEVICES
1 PRECAUTION AGAINST ESD FOR MOS DEVICES
Exposing the MOS devices to a strong electric field can cause destruction of the gate
oxide and ultimately degrade the MOS devices operation. Steps must be taken to stop
generation of static electricity as much as possible, and quickly dissipate it, when once
it has occurred. Environmental control must be adequate. When it is dry, humidifier
should be used. It is recommended to avoid using insulators that easily build static
electricity. MOS devices must be stored and transported in an anti-static container,
static shielding bag or conductive material. All test and measurement tools including
work bench and floor should be grounded. The operator should be grounded using
wrist strap. MOS devices must not be touched with bare hands. Similar precautions
need to be taken for PW boards with semiconductor MOS devices on it.
2 HANDLING OF UNUSED INPUT PINS FOR CMOS DEVICES
No connection for CMOS devices input pins can be a cause of malfunction. If no
connection is provided to the input pins, it is possible that an internal input level may be
generated due to noise, etc., hence causing malfunction. CMOS devices behave
differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed
high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected
to VDD or GND with a resistor, if it is considered to have a possibility of being an output
pin. The unused pins must be handled in accordance with the related specifications.
3 STATUS BEFORE INITIALIZATION OF MOS DEVICES
Power-on does not necessarily define initial status of MOS devices. Production process
of MOS does not define the initial operation status of the device. Immediately after the
power source is turned ON, the MOS devices with reset function have not yet been
initialized. Hence, power-on does not guarantee output pin levels, I/O settings or
contents of registers. MOS devices are not initialized until the reset signal is received.
Reset operation must be executed immediately after power-on for MOS devices having
reset function.
CME0107
Preliminary Data Sheet E0253N10 (Ver. 1.0)
12

12 Page





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