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PDF MC-45V8AB641 Data sheet ( Hoja de datos )
| Número de pieza | MC-45V8AB641 | |
| Descripción | 8M-WORD BY 64-BIT VirtualChannel SYNCHRONOUS DYNAMIC RAM MODULE UNBUFFERED TYPE | |
| Fabricantes | NEC | |
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DATA SHEET
MOS INTEGRATED CIRCUIT
MC-45V8AB641
8M-WORD BY 64-BIT
VirtualChannelTM SYNCHRONOUS DYNAMIC RAM MODULE
UNBUFFERED TYPE
Description
The MC-45V8AB641 is a 8,388,608 words by 64 bits VirtualChannel synchronous dynamic RAM module on which 4
pieces of 128M VirtualChannel SDRAM : µPD45125161 are assembled.
This module provides high density and large quantities of memory in a small space without utilizing the surface-
mounting technology on the printed circuit board.
Decoupling capacitors are mounted on power supply line for noise reduction.
Features
• 8,388,608 words by 64 bits organization
• Clock frequency and access time from CLK
Part number
Read Clock
Access
Maximum supply current mA
latency frequency time
Operating
MHz (MAX.) from CLK Prefetch Restore
Channel
ns (MAX.)
read / write (Burst)
• MC-45V8AB641KFA-A75 2
133
5.4
600
300
• MC-45V8AB641KFA-A10
100 6
520
300
Refresh
Auto
Self
920 8
880
• Fully Standard Synchronous Dynamic RAM, with all signals referenced to a positive clock edge
• Dual internal banks controlled by BA0 (Bank Select)
• Programmable wrap sequence (sequential / interleave)
• Programmable burst length (1, 2, 4, 8 and 16)
• • Read latency (2)
• • Prefetch read latency (4)
• Auto precharge and without auto precharge
• Auto refresh and self refresh
• Single 3.3 V ± 0.3 V power supply
• Interface: LVTTL
• Refresh cycle: 4K cycles/64 ms
• 168-pin dual in-line memory module (Pin pitch = 1.27 mm)
• Unbuffered type
• Serial PD
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for
availability and additional information.
Document No. M14619EJ2V0DS00 (2nd edition)
Date Published June 2000 NS CP (K)
Printed in Japan
The mark • shows major revised points.
©
1999
1 page  
MC-45V8AB641
Electrical Specifications
• All voltages are referenced to VSS (GND).
• After power up, wait more than 100 µs and then, execute power on sequence and auto refresh before proper device
operation is achieved.
Absolute Maximum Ratings
Parameter
Voltage on power supply pin relative to GND
Voltage on input pin relative to GND
Short circuit output current
Power dissipation
Operating ambient temperature
Storage temperature
Symbol
VCC
VT
IO
PD
TA
Tstg
Condition
Rating
–0.5 to +4.6
–0.5 to +4.6
50
4
0 to +70
–55 to +125
Unit
V
V
mA
W
°C
°C
Caution Exposing the device to stress above those listed in Absolute Maximum Ratings could cause
permanent damage. The device is not meant to be operated under conditions outside the limits
described in the operational section of this specification. Exposure to Absolute Maximum Rating
conditions for extended periods may affect device reliability.
Recommended Operating Conditions
Parameter
Supply voltage
High level input voltage
Low level input voltage
Operating ambient temperature
Symbol
VCC
VIH
VIL
TA
Condition
MIN.
3.0
2.0
−0.3
0
TYP.
3.3
MAX.
3.6
VCC + 0.3
+0.8
70
Unit
V
V
V
°C
Capacitance (TA = 25 °C, f = 1 MHz)
Parameter
Input capacitance
Data input/output capacitance
Symbol
CI1
CI2
CI3
CI4
CI5
CI/O
Test condition
A0 - A12, BA0 (A13), /RAS, /CAS, /WE
CLK0, CLK2
CKE0
/CS0, /CS2
DQMB0 - DQMB7
DQ0 - DQ63
MIN.
22
24
22
12
7
7
TYP.
MAX.
40
40
40
20
13
13
Unit
pF
pF
Data Sheet M14619EJ2V0DS00
5
5 Page 
MC-45V8AB641
Serial PD
(1/2)
Byte No.
Function Described
0 Defines the number of bytes written
into serial PD memory
1 Total number of bytes of serial PD
memory
2 Fundamental memory type
Hex Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Notes
80H 1 0 0 0 0 0 0 0 128 bytes
08H 0 0 0 0 1 0 0 0 256 bytes
08H 0 0 0 0 1 0 0 0 VC SDRAM
3 Number of row addresses
0DH 0 0 0 0 1 1 0 1 13 rows
4 Number of column addresses
07H 0 0 0 0 0 1 1 1 7 columns
5 Number of banks
01H 0 0 0 0 0 0 0 1 1 bank
6 Data width
40H 0 1 0 0 0 0 0 0 64 bits
7 Data width (continued)
00H 0 0 0 0 0 0 0 0 0
8 Voltage interface standard
01H 0 0 0 0 0 0 0 1 LVTTL
9 Read latency (/CAS latency) = 2 -A75 75H 0 1 1 1 0 1 0 1 7.5 ns
cycle time
-A10 A0H 1 0 1 0 0 0 0 0 10 ns
10 Read latency (/CAS latency) = 2 -A75 54H 0 1 0 1 0 1 0 0 5.4 ns
access time
-A10 60H 0 1 1 0 0 0 0 0 6 ns
11 DIMM configuration type
00H 0 0 0 0 0 0 0 0 None
12 Refresh rate / type
80H 1 0 0 0 0 0 0 0 Normal
13 VC SDRAM width
10H 0 0 0 1 0 0 0 0 ×16
14 Error checking SDRAM width
00H 0 0 0 0 0 0 0 0 None
15 Minimum clock delay
01H 0 0 0 0 0 0 0 1 1 clock
16 Burst length supported
1FH 0 0 0 1 1 1 1 1 1, 2, 4, 8, 16
17 Number of banks on each VC SDRAM 02H 0 0 0 0 0 0 1 0 2 banks
• 18 Read latency (/CAS latency) supported 02H 0 0 0 0 0 0 1 0 2
19 /CS latency supported
01H 0 0 0 0 0 0 0 1 0
20 /WE latency supported
01H 0 0 0 0 0 0 0 1 0
21 VC SDRAM module attributes
00H 0 0 0 0 0 0 0 0
22 VC SDRAM device attributes : general 0EH 0 0 0 0 1 1 1 0
• 23-26
00H 0 0 0 0 0 0 0 0
27 tRP (MIN.)
-A75 14H 0 0 0 1 0 1 0 0 20 ns
-A10 14H 0 0 0 1 0 1 0 0 20 ns
28 tRRD (MIN.)
-A75 0FH 0 0 0 0 1 1 1 1 15 ns
-A10 14H 0 0 0 1 0 1 0 0 20 ns
29 tAPD (MIN.)
-A75 0FH 0 0 0 0 1 1 1 1 15 ns
-A10 14H 0 0 0 1 0 1 0 0 20 ns
30 tRAS (MIN.)
-A75 34H 0 0 1 1 0 1 0 0 52.5 ns
-A10 3CH 0 0 1 1 1 1 0 0 60 ns
Data Sheet M14619EJ2V0DS00
11
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