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MC-4564EC726 Schematic ( PDF Datasheet ) - NEC

Teilenummer MC-4564EC726
Beschreibung 64 M-WORD BY 72-BIT SYNCHRONOUS DYNAMIC RAM MODULE REGISTERED TYPE
Hersteller NEC
Logo NEC Logo 




Gesamt 16 Seiten
MC-4564EC726 Datasheet, Funktion
DATA SHEET
MOS INTEGRATED CIRCUIT
MC-4564EC726
64 M-WORD BY 72-BIT SYNCHRONOUS DYNAMIC RAM MODULE
REGISTERED TYPE
Description
The MC-4564EC726 is a 67,108,864 words by 72 bits synchronous dynamic RAM module on which 36 pieces of
128 M SDRAM: µPD45128441 are assembled.
These modules provide high density and large quantities of memory in a small space without utilizing the surface-
mounting technology on the printed circuit board.
Decoupling capacitors are mounted on power supply line for noise reduction.
Features
67,108,864 words by 72 bits organization (ECC type)
Clock frequency and access time from CLK
Part number
/CAS latency
Clock frequency
(MAX.)
Access time from CLK
(MAX.)
Module type
MC-4564EC726EFB-A80
CL = 3
125 MHz
6 ns PC100 Registered DIMM
CL = 2
100 MHz
6 ns Rev. 1.2 Compliant
MC-4564EC726EFB-A10
CL = 3
100 MHz
6 ns
5 MC-4564EC726PFB-A80
CL = 2
CL = 3
77 MHz
125 MHz
7 ns
6 ns
CL = 2
100 MHz
6 ns
5 MC-4564EC726PFB-A10
CL = 3
100 MHz
6 ns
CL = 2
77 MHz
7 ns
Fully Synchronous Dynamic RAM, with all signals referenced to a positive clock edge
Pulsed interface
Possible to assert random column address in every cycle
Quad internal banks controlled by BA0 and BA1 (Bank Select)
Programmable burst-length (1, 2, 4, 8 and Full Page)
Programmable wrap sequence (Sequential / Interleave)
Programmable /CAS latency (2, 3)
Automatic precharge and controlled precharge
CBR (Auto) refresh and self refresh
All DQs have 10 Ω ± 10 % of series resistor
Single 3.3 V ± 0.3 V power supply
LVTTL compatible
4,096 refresh cycles / 64 ms
Burst termination by Burst Stop command and Precharge command
168-pin dual in-line memory module (Pin pitch = 1.27 mm)
Registered type
Serial PD
Stacked monolithic technology
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for
availability and additional information.
Document No. M14460EJ2V0DS00 (2nd edition)
Date Published February 2000 NS CP(K)
Printed in Japan
The mark 5 shows major revised points.
©
1999






MC-4564EC726 Datasheet, Funktion
MC-4564EC726
Electrical Specifications
All voltages are referenced to VSS (GND).
After power up, wait more than 1 ms and then, execute power on sequence and CBR (Auto) refresh before proper
device operation is achieved.
Absolute Maximum Ratings
Parameter
Voltage on power supply pin relative to GND
Voltage on input pin relative to GND
Short circuit output current
Power dissipation
Operating ambient temperature
Storage temperature
Symbol
VCC
VT
IO
PD
TA
Tstg
Condition
Rating
–0.5 to +4.6
–0.5 to +4.6
50
40
0 to 70
–55 to +125
Unit
V
V
mA
W
°C
°C
Caution
Exposing the device to stress above those listed in Absolute Maximum Ratings could cause
permanent damage. The device is not meant to be operated under conditions outside the limits
described in the operational section of this specification. Exposure to Absolute Maximum Rating
conditions for extended periods may affect device reliability.
Recommended Operating Conditions
Parameter
Supply voltage
High level input voltage
Low level input voltage
Operating ambient temperature
Symbol
VCC
VIH
VIL
TA
Condition
MIN.
3.0
2.0
–0.3
0
TYP.
3.3
MAX.
3.6
VCC + 0.3
+0.8
70
Unit
V
V
V
°C
Capacitance (TA = 25 °C, f = 1 MHz)
Parameter
Symbol
Test condition
Input capacitance
5
CI1 A0 - A11, BA0 (A13), BA1 (A12),
/RAS, /CAS, /WE
CI2 CLK0
CI3 CKE0
CI4 /CS0 - /CS3
CI5 DQMB0 - DQMB7
Data input/output capacitance
CI/O DQ0 - DQ63, CB0 - CB7
MIN.
TBD
TYP.
MAX.
TBD
Unit
pF
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
pF
6 Data Sheet M14460EJ2V0DS00

6 Page









MC-4564EC726 pdf, datenblatt
MC-4564EC726
(2/2)
Byte No.
Function Described
Hex Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Notes
32 Command and address signal input
20H 0 0 1 0 0 0 0 0 2 ns
setup time
33 Command and address signal input hold 10H 0 0 0 1 0 0 0 0 1 ns
time
34 Data signal input setup time
20H 0 0 1 0 0 0 0 0 2 ns
35 Data signal input hold time
10H 0 0 0 1 0 0 0 0 1 ns
36-61
00H 0 0 0 0 0 0 0 0
62 SPD revision
63 Checksum for bytes 0 - 62
12H 0 0 0 1 0 0 1 0 1.2 A
-A80 3BH 0 0 1 1 1 0 1 1
-A10 A1H 1 0 1 0 0 0 0 1
64-71 Manufacture’s JEDEC ID code
72 Manufacturing location
73-90 Manufacture’s P/N
91 Revision Code
93-94 Manufacturing date
95-98 Assembly serial number
99-125 Mfg specific
126 Intel specification frequency
64H 0 1 1 0 0 1 0 0 100 MHz
127 Intel specification /CAS
latency support
-A80 87H 1 0 0 0 0 1 1 1
-A10 85H 1 0 0 0 0 1 0 1
Timing Chart
Refer to the SYNCHRONOUS DRAM MODULE TIMING CHART Information (M13348E).
12 Data Sheet M14460EJ2V0DS00

12 Page





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