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PDF LS7166 Data sheet ( Hoja de datos )
| Número de pieza | LS7166 | |
| Descripción | 24-BIT QUADRATURE COUNTER | |
| Fabricantes | LSI Computer Systems | |
| Logotipo |  |
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LSI/CSI
LS7166
U® L LSI Computer Systems, Inc. 1235 Walt Whitman Road, Melville, NY 11747 (631) 271-0400 FAX (631) 271-0405
A3800
24-BIT QUADRATURE COUNTER
December 2008
FEATURES:
• Programmable modes are: Up/Down,
Binary, BCD, 24 Hour Clock, Divide-by-N,
x1 or x2 or x4 Quadrature and Single-Cycle.
• DC to 25MHz Count Frequency.
• 8-Bit I/O Bus for uP Communication and Control.
• 24-Bit comparator for pre-set count comparison.
• Readable status register.
• Input/Output TTL and CMOS compatible.
• 3V to 5.5V operation (VDD - VSS).
• LS7166 (DIP); LS7166-S (SOIC);
LS7166-TS24 (24-Pin TSSOP) - See Figure 1 -
GENERAL DESCRIPTION:
The LS7166 is a CMOS, 24-bit counter that can be pro-
grammed to operate in several different modes. The oper-
ating mode is set up by writing control words into internal
control registers (see Figure 8). There are three 6-bit and
one 2-bit control registers for setting up the circuit functional
characteristics. In addition to the control registers, there is a
5-bit output status register (OSR) that indicates the current
counter status. The IC communicates with external circuits
through an 8-bit three state I/O bus. Control and data words
are written into the LS7166 through the bus. In addition to
the I/O bus, there are a number of discrete inputs and out-
puts to facilitate instantaneous hardware based control func-
tions and instantaneous status indication.
REGISTER DESCRIPTION:
Internal hardware registers are accessible through the I/O
bus (D0 - D7) for READ or WRITE when CS = 0. The C/D in-
put selects between the control registers (C/D = 1) and the
data registers (C/D = 0) during a READ or WRITE operation.
(See Table 1)
The information included herein is believed to be
accurate and reliable. However, LSI Computer Systems,
Inc. assumes no responsibilities for inaccuracies, nor for
any infringements of patent rights of others which may
result from its use.
PIN ASSIGNMENTS - Top View
20-PIN
DIP and SOIC
WR 1
20 VSS ( -V )
CS 2
LCTR/LLTC 3
19 RD
18 C/D
ABGT/RCTR 4
17 BW
VDD ( +V) 5
16 CY
A6
15 D7
B7
14 D6
D0 8
13 D5
D1 9
12 D4
D2 10
11 D3
WR 1
CS 2
LCTR/LLTC
3
ABGT/RCTR
4
NC 5
NC 6
NC 7
A8
B9
D0 10
D1 11
D2 12
24-PIN
TSSOP
24 VSS ( - V )
23 RD
22 C/D
21 VDD ( +V)
20 BW
19 CY
18 NC
17 D7
16 D6
15 D5
14 D4
13 D3
FIGURE 1
7166-121508-1
1 page  
I/O DESCRIPTION:
(See REGISTER DESCRIPTION for I/O Prgramming.)
Data-Bus (D0 - D7) (Pin 8 - Pin 15). The 8-line data bus is a
three-state I/O bus for interfacing with the system bus.
CS (Chip Select Input) (Pin 2). A logical "0" at this input enables
the chip for Read and Write.
RD (Read Input) (Pin 19). A logical "0" at this input enables the
OSR and the OL to be read on the data bus.
WR (Write Input) (Pin 1). A logical "0" at this input enables the
data bus to be written into the control and data registers.
C/D (Control/Data Input) (Pin 18). A logical "1" at this input en-
ables a control word to be written into one of the four control reg-
isters or the OSR to be read on the I/O bus. A logical "0" enables
a data word to be written into the PR, or the OL to be read on the
I/O bus.
A (Pin 6). Input A is a programmable count input capable of
functioning in three different modes, such as up count input, down
count input and quadrature input. In non-quadrature mode, the
counter advances on the rising edge of Input A
B (Pin 7). Input B is also a programmable count input that can be
programmed to function either as down count input, or count
direction control gate for input A, or quadrature input. In non- quad-
rature mode, and when programmed as the Down Count input, the
counter advances on the rising edge of Input B. When B is pro-
grammed as the count direction control gate, B = 0 enables A as
the Up Count input and B = 1 enables A as the Down Count input.
When programmed as the direction input, B can switch state only
when A is high.
ABGT/RCTR (Pin 4). This input can be programmed to function
as either inputs A and B enable gate or as external counter reset
input. A logical "0" is the active level on this input. In non-
quadrature mode, if Pin 4 is programmed as A and B enable gate
input, it may switch state only when A is high (if A is clock and B
is direction) or when both A and B are high (if A and B are
clocks). In quadrature mode, if Pin 4 is programmed as A and B
enable gate, it may switch state only when either A or B switches.
LCTR/LLTC (Pin 3 ) This input can be programmed to function
as the external load command input for either the CNTR or the
OL. When programmed as counter load input, the counter is
loaded with the data contained in the PR. When programmed as
the OL load input, the OL is loaded with data contained in the
CNTR. A logical "0" is the active level on this input.
CY (Pin 16) This output can be programmed to serve as one of
the following:
A. CY. Complemented Carry out (active "0").
B. CY. True Carry out (active "1").
C. CYT. Carry Toggle flip-flop out.
D. COMP. Comparator out (active "0")
BW (Pin 17) This output can be programmed to serve as one of
the following:
A. BW. Complemented Borrow out (active "0").
B. BW. True Borrow out (active "1").
C. BWT. Borrow Toggle flip-flop out.
D. COMPT. Comparator Toggle output.
VDD (Pin 5) Supply voltage positive terminal.
VSS (Pin 20) Supply voltage negative terminal.
Absolute Maximum Ratings:
Parameter
Voltage at any input
Symbol
VIN
Operating Temperature
TA
Storage Temperature
Supply Voltage
TSTG
VDD - VSS
Values
VSS - 0.3 to VDD + 0.3
-40 to +125
-65 to +150
+7.0
Unit
V
oC
oC
V
DC Electrical Characteristics. (All voltages referenced to VSS.
TA = 0˚ to 85˚C, VDD = 3V to 5.5V, fc = 0, unless otherwise specified)
Parameter
Supply Voltage
Supply Current
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
Input Current
Symbol
VDD
IDD
VIL
VIH
VOL
VOH
-
Min. Value
3.0
-
0
2.0
-
2.5
-
Max.Value
5.5
350
0.8
VDD
0.4
-
15
Output Source Current
Output Sink Current
Data Bus Off-State
Leakage Current
ISRC
ISINK
-
200
4
-
-
-
15
Unit
V
µA
V
V
V
V
nA
µA
mA
nA
Remarks
-
Outputs open
-
-
4mA Sink, VDD = 5V
200µA Source, VDD = 5V
Leakage
Current
VOH = 2.5V, VDD = 5V
VOL = 0.4V, VDD = 5V
-
7166-082906-5
5 Page 
FIGURE 9. 80C31/8051 TO LS7166 INTERFACE IN EXTERNAL ADDRESS MODE
8051
80C31
P0.0
P0.1
P0.2
P0.3
P0.4
P0.5
P0.6
P0.7
ALE
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
74HC573
2
3
D1
4
5
6
7
8
9
11
D2
D3
D4
D5
D6
D7
D8
C
1 0C
Q1
Q8
19
12
7166
18 C/D
2 CS/
7166-110503-11
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
8 D0
9 D1
10 D2
11 D3
12 D4
13 D5
14 D6
15 D7
WR/
RD/
1 WR/
19 RD/
NOTE: Port_0 is open drain output. Add pull-up resistors to all Port_0 i/0 lines.
11 Page | ||
| Páginas | Total 19 Páginas | |
| PDF Descargar | [ Datasheet LS7166.PDF ] | |
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