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PDF LRS1302 Data sheet ( Hoja de datos )
| Número de pieza | LRS1302 | |
| Descripción | Stacked Chip 8M Flash and 1M SRAM | |
| Fabricantes | Sharp | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de LRS1302 (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
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PRODUCT SPECIFICATIONS
®
Integrated Circuits Group
LRS1302
Stacked Chip
8M Flash and 1M SRAM
(Model No.: LRS13023)
Spec No.: EL116039
Issue Date: June 11, 1999
1 page  
5 Page 
SHARP
LRS13023
9
INTRODUCTION
his datasheet contains LRS1302 specifications.
iection 1 provides a flash memory overview. Sections
!, 3,4, and 5 describe the memory organization and
unctiordity. Section 6 covers electrical specifications.
..l New Features
The LRS1302 SmartVoltage Flash memory maintains
)ackwards-compatibility
with SHARP’s 28F008SA.
Cey enhancements over the 28F008SA include:
SmartVoltage Technology
*Enhanced Suspend Capabilities
Jn-System Block Locking
30th devices share a compatible, status register, and
oftware command set. These similarities enable a
clean upgrade from the 28FOO8SA to LRS1302. When
upgrading, it is important to note the following
iifferences:
-Because of new feature support, the two devices
have different device codes. This allows for
software optimization.
.VPpLK has been lowered from 6SV to 1.5V to
support 2.7V-3.6V block erase, byte write, and
lock-bit configuration operations. Designs that
switch VPP off during read operations should make
sure that the VP, voltage transitions to GND.
*To take advantage of SmartVoltage technology,
allow VP, connection to 2.7V-3.6V.
I.2 Product Overview
The LRS1302 is a high-performance
&Mbit
;martVoltage Flash memory organized as 1 Mbyte of 8
>its. The 1 Mbyte of data is arranged in sixteen
&Kbyte blocks which are individually erasable,
o&able, and unlockable in-system. The memory map
s shown in Figure 2.
SmartVoltage technology provides a choice of Vcc and
VP, combinations, as shown in Table 1, to meet system
performance and power expectations. V, at 2.7V to
3.6V eliminates the need for a separate 12V converter.
In addition to flexible erase and program voltages, the
dedicated VPP pm gives complete data protection
when VP, I VP,,.
Table 1. V,, and VP, Voltage Combinations Offered
by SmartVoltage Technology
;_. Vcc Voltage
VPP Voltage
2,7V to 3.6V(‘l)
NOTE’ ’
2.7V to 3.6V
I
‘1. FLASH Erase/Write(T*=O”C to 85°C)
Internal Vcc and VW detection Circuitry
automatically configures the device for optimized read
and write operations.
A Command User Interface (CUT) serves as the
interface between the system processor and internal
operation of the device. A valid command sequence
written to the CUT initiates device automation. An
internal Write State Machine (WSM) automatically
executes the algorithms and timings necessary for
block erase, byte write, and lock-bit configuration
operations.
A block erase operation erases one of the device’s
64Kbyte blocks typically within 1.8 second
independent of other blocks. Each block can be
independently erased 100,000 times (1.6 million block
erases per device). Block erase suspend mode allows
system software to suspend block erase to read or
write data from any other block.
Writing memory data is performed in byte increments
typically within 17 us. Byte write suspend mode
enables the system to read data or execute code from
any other flash memory a1rray location.
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet LRS1302.PDF ] | |
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