PDF LMX2471 Data sheet ( Hoja de datos )

Número de pieza	LMX2471
Descripción	3.6 GHz Delta-Sigma Fractional-N PLL with 1.7 GHz Integer-N PLL
Fabricantes	National Semiconductor
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No Preview Available ! November 2003 LMX2471 3.6 GHz Delta-Sigma Fractional-N PLL with 1.7 GHz Integer-N PLL General Description The LMX2471 is a low power, high performance delta-sigma fractional-N PLL with an auxiliary integer-N PLL. The device is fabricated using National Semiconductor’s advanced BiC- MOS process. With delta-sigma architecture, fractional spur compensation is achieved with noise shaping capability of the delta-sigma modulator and the inherent low pass filtering of the PLL loop filter. Fractional spurs at lower frequencies are pushed to higher frequencies outside the loop bandwidth. Unlike ana- log compensation, the digital feedback techniques used in the LMX2471 are highly resistant to changes in temperature and variations in wafer processing. With delta-sigma archi- tecture, the ability to push close in spur and phase noise energy to higher frequencies is a direct function of the modu- lator order. The higher the order, the more this energy can be spread to higher frequencies. The LMX2471 has a program- mable modulator up to order four, which allows the designer to select the optimum modulator order to fit the phase noise, spur, and lock time requirements of the system. Programming is fast and simple. Serial data is transferred into the LMX2471 via a three line MICROWIRE interface (Data, Clock, Load Enable). Nominal supply voltage is 2.5 V. The LMX2471 features a typical current consumption of 5.6 mA at 2.5 V. The LMX2471 is available in a 24 lead 3.5 X 4.5 X 0.6 mm package. Features n Low in-band phase noise and low fractional spurs n 12 bit or 22 bit selectable fractional modulus n Up to 4th order programmable delta-sigma modulator n Enhanced Anti-Cycle Slip Fastlock Circuitry Fastlock Cycle slip reduction Integrated timeout counters n Digital lock detect output n Prescalers allow wide range of N values RF PLL: 16/17/20/21 IF PLL: 8/9 or 16/17 n Crystal Reference Frequency up to 110 MHz n On-chip crystal reference frequency doubler. n Phase Comparison Frequency up to 50 MHz n Hardware and software power-down control n Ultra low consumption: ICC = 5.6 mA (typical) Applications n Cellular Phones and Base Stations n Applications requiring fine frequency resolution n Satellite and Cable TV Tuners n WLAN Standards Functional Block Diagram © 2003 National Semiconductor Corporation DS200721 20072101 www.national.com 1 page Electrical Characteristics (VCC = 2.5V; -40˚C ≤ TA ≤ +85˚C unless otherwise specified) (Continued) Symbol Parameter Conditions DIGITAL INTERFACE (DATA, CLK, LE, EN, ENRF, Ftest/LD, FLoutRF, FLoutIF) VOL Low-Level Output Voltage MICROWIRE INTERFACE TIMING IOL = 500 µA TCS TCH TCWH TCWL TES Data to Clock Set Up Time Data to Clock Hold Time Clock Pulse Width High Clock Pulse Width Low Clock to Load Enable Set Up Time See Microwire Input Timing See Microwire Input Timing See Microwire Input Timing See Microwire Input Timing See Microwire Input Timing TEW Load Enable Pulse Width PHASE NOISE See Microwire Input Timing LF1HzRF RF Synthesizer Normalized Phase Noise Contribution (Note 3) RF_CPG = 0 RF_CPG = 3 RF_CPG = 7 RF_CPG = 15 LF1HzIF IF Synthesizer Normalized Phase Noise Contribution Applies to both low and high current modes (Note 3) OSC=0 Min 50 10 50 50 50 50 Value Typ -200 -206 -208 -210 -214 Max Units 0.4 V ns ns ns ns ns ns dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz Note 3: Normalized Phase Noise Contribution is defined as: LN(f) = L(f) – 20log(N) – 10log(fCOMP) where L(f) is defined as the single side band phase noise measured at an offset frequency, f, in a 1 Hz Bandwidth. The offset frequency, f, must be chosen sufficiently smaller than the PLL loop bandwidth, yet large enough to avoid substantial phase noise contribution from the reference source. The offset chosen was 4 KHz. MICROWIRE INPUT TIMING DIAGRAM 20072172 Note 4: Note that although it is valid return the CLK, DATA, and LE pins to a high state after programming is complete, this is not the preferred method. One problem with keeping these pins at a high voltage is that there is increased leakage through these pins if they are not grounded. Also, the action of returning the CLK pin to a high voltage after programming is finished can create an extra clock cycle that can cause problems if it is done too soon after the LE pin voltage is returned to a high state. If possible, it is best to return all microwire pins to 0 V when the PLL is not being programmed in order to avoid these issues with leakage and timing. 5 www.national.com 5 Page Typical Performance Characteristic : OSCin Input Impedance (Note 6) Frequency (MHz) 50 10 20 30 40 50 60 70 80 90 100 110 OSCin Input Impedance (VCC=2.5 V, TA=25 ˚C) (Note 5) Real (Ohms) Imaginary (Ohms) 2200 -4700 710 -2700 229 -1500 133 -988 93 -752 74 -606 62 -505 53 -435 49 -382 45 -341 42 -309 40 -282 20072155 Magnitude (Ohms) 5189 2792 1517 997 758 611 509 438 385 344 312 285 11 www.national.com 11 Page

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