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IA64250-PLC68M Schematic ( PDF Datasheet ) - InnovASIC

Teilenummer IA64250-PLC68M
Beschreibung Histogram/Hough Transform Processor
Hersteller InnovASIC
Logo InnovASIC Logo 




Gesamt 21 Seiten
IA64250-PLC68M Datasheet, Funktion
IA64250
Histogram/Hough Transform Processor
FEATURES
Histogram and Hough Transform Calculation
Data Sheet
As of Production Ver. 01
Four 512 X 9 Look-up Tables Provided to Perform User-defined Point-wise
Transformations
Real-time Histogram Equalization
High Data Rates
512 X 24 Accumulation RAM
Pixel Location Function
The IA64250 is a "plug-and-play" drop-in replacement for the original LSI® L64250. This replacement IC
has been developed using innovASIC’s MILESTM, or Managed IC Lifetime Extension System, cloning
technology. This technology produces replacement ICs far more complex than "emulation" while ensuring
they are compatible with the original IC. MILESTM captures the design of a clone so it can be produced even
as silicon technology advances. MILESTM also verifies the clone against the original IC so that even the
"undocumented features" are duplicated. This data sheet documents all necessary engineering information
about the IA64250 including functional and I/O descriptions, electrical characteristics, and applicable timing.
Package Pinout for 68 PLCC PACKAGE:
9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61
10 60
11 59
12 58
13 57
14 56
15 55
16 54
17 53
18 52
19 51
20 50
21 49
22 48
23 47
24 46
25 45
26 44
27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
Copyright © 2000
innovASIC
The End of Obsolescence
ENG211001219-01
Page 1 of 21
www.innovasic.com
Customer Support:
1-888 -824-4184






IA64250-PLC68M Datasheet, Funktion
IA64250
Histogram/Hough Transform Processor
Data Sheet
As of Production Ver. 01
INITIALIZATION MODE:
Initialization defines the operation of the IA64250. The mode and marker memories store
66 nine-bit words that define the operation of the part and contain marker information. The
REGADR input is used to select the proper register. Data is written over the CI bus and
read on the DO bus. The AT pin controls whether data is a mode word or a marker. When
AT is low, the data written is mode information, which is stored in the mode registers
contained in the controller block. When AT is high, the data is a marker, and is stored in the
marker memory. To prevent erroneous operation STARTIOn should be high, and IODV
and DV should be low during initialization.
Mode Register Table:
A REGA R/ BIT LOCATION
T DR
W
W ci0 ci1 ci2
R do0 do1 do2
00
W sel0 sel1 sel2
01
W fn0 fn1 Eq
ci3 ci4 ci5
do3 do4 do5
sel3 lut0 lut1
io0 io1 hclr0
ci6
do6
sh1
hclr1
ci7 ci8
do7 do8
sat TESTn
func pdwn
Marker Memory Table:
AT REGADR
10
11
12
13
R/W
R
R
R
R
CONTENTS
GREY LEVEL OF MAXIMUM ACC COUNT BITS 0-8
MAXIMUM ACC COUNT BITS 0-8
MAXIMUM ACC COUNT BITS 9-17
MAXIMUM ACC COUNT BITS 18-23*
1 16
1 17
1 18
1 19
W TEST MODE, DO NOT ACCESS
W TEST MODE, DO NOT ACCESS
W TEST MODE, DO NOT ACCESS
W TEST MODE, DO NOT ACCESS
1 32
1 33
1 34
1 35
R/W
R/W
R/W
R/W
R/W MARKER 0 GREY LEVEL BITS 0-8
R/W MARKER 0 ACC COUNT BITS 0-8
R/W MARKER 0 ACC COUNT BITS 9-17
R/W MARKER 0 ACC COUNT BITS 18-23*
1 36
R/W
R/W MARKER 1 GREY LEVEL BITS 0-8
1 37
R/W
R/W MARKER 1 ACC COUNT BITS 0-8
1 38
R/W
R/W MARKER 1 ACC COUNT BITS 9-17
1 39
R/W
R/W MARKER 1 ACC COUNT BITS 18-23*
.
.
.
1 56
R/W
R/W MARKER 6 GREY LEVEL BITS 0-8
1 57
R/W
R/W MARKER 6 ACC COUNT BITS 0-8
1 58
R/W
R/W MARKER 6 ACC COUNT BITS 9-17
1 59
R/W
R/W MARKER 6 ACC COUNT BITS 18-23*
*ACC COUNT BIT 18-23 APPEARS ON BIT LOCATION 0-5 RESPECTIVELY
Copyright © 2000
innovASIC
The End of Obsolescence
ENG211001219-01
Page 6 of 21
www.innovasic.com
Customer Support:
1-888 -824-4184

6 Page









IA64250-PLC68M pdf, datenblatt
IA64250
Histogram/Hough Transform Processor
Data Sheet
As of Production Ver. 01
coordinates are stored in the ACC RAM. Storage space is assigned sequentially as defined by
the FP counter.
I/O Mode:
Once a computation has taken place, the user reads data from the LUT or the ACC RAM.
These operations typically take place during a vertical retrace or some other period when the
processor is not busy and AT is low. This mode is also to load the LUT with the desired
transfer function. Generally, these operations are controlled by CLK2 so that data may be
read or written at a different rate than the pixel clock. If the ACC RAM is accessed, the
marker values will be updated.
The internal signals hclr(1:0) control whether or not the ACC RAM is cleared during I/O
operations. These values are stored in the mode registers of the controller block during the
initialization mode. If both hclr0 and hclr1 are high then the ACC RAM will not be cleared
during any I/O operation. If hclr0 is high and hclr1 is low, then each ACC RAM location
will be cleared after it is read. If both hclr0 and hclr1 are low then each ACC RAM location
is cleared when either the ACC RAM location or the corresponding LUT RAM location is
accessed.
Read/Transfer ACC RAM:
Once the histogram has been computed and stored in the ACC RAM, the user asserts
STARTIOn low to initiate reading of the data. One data value is read out of the ACC RAM
during each clock cycle of CLK2 starting with address 0. The address counter for the ACC
RAM is contained in the controller block. If STARTIO remains low, all 512 data values will
be read in sequential address order and the processor will return to pixel processing mode
after 512 clock cycles. If STARTIOn is returned high, the I/O mode halts and the user can
return to pixel processing operations. When the output flag IODV is high, the processor
has placed valid data from the LUT or ACC RAMs onto the I/O bus.
The user controls the destination of the ACC RAM data via the io(1:0) bits in the mode
registers located in the control memory. Code 01 signifies that histogram data will be placed
on the DO output bus, while code 00 will transfer data from the ACC RAM to the LUT
RAM.
In both cases the user can modify the histogram data. By setting the internal EQ control bit
high, an accumulated histogram will be output. The shifter allows the user to determine
which nine bits of the 24 bit ACC RAM output will be directed to the DO bus and LUT
RAM. The shifter control data is stored in the mode registers. The control signals for the
shifter are generated in the controller block. Additional control over the output format can
be obtained via the SAT pin in the control memory. When SAT is high, the resultant nine
bit shifted output will be forced to 511 (111111111) if overflow occurs in the shifter.
Copyright © 2000
innovASIC
The End of Obsolescence
ENG211001219-01
Page 12 of 21
www.innovasic.com
Customer Support:
1-888 -824-4184

12 Page





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