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PDF HYS64V64220GBDL Data sheet ( Hoja de datos )
| Número de pieza | HYS64V64220GBDL | |
| Descripción | 144 pin SO-DIMM SDRAM Modules | |
| Fabricantes | Infineon | |
| Logotipo |  |
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144 pin SO-DIMM SDRAM Modules
HYS64V64220GBDL-7/7.5/8-D
512 MB PC100 / PC133
• u144 Pin Eight Byte Small Outline Dual-In-Line Synchronous DRAM Modules
for notebook applications
• Two bank 64M x 64 non-parity module organisation
• suitable for use in PC100 and PC133 applications
• Performance:
fCK Clock frequency (max.)
tAC Clock access time
CAS latency = 2 & 3
-7
PC133
2-2-2
133
5.4
-7.5
PC133
3-3-3
133
5.4
-8
PC100
2-2-2
100
6
Units
MHz
ns
• Single +3.3V(± 0.3V ) power supply
• Programmable CAS Latency, Burst Length and Wrap Sequence
(Sequential & Interleave)
• Auto Refresh (CBR) and Self Refresh
• Decoupling capacitors mounted on substrate
• All inputs, outputs are LVTTL compatible
• Serial Presence Detect with E2PROM
• Uses sixteen 256Mbit SDRAM (32Mb x8 ) components in P-TFBGA packages
• 8196 refresh cycles every 64 ms
• Gold contact pad, JEDEC MO-190 outline dimensions
• This module family is fully pin and functional compatible
with the latest INTEL SO-DIMM specification
• Importante Notice:
This SO-DIMM module is based on 256Mbit SDRAM technology and can be
used in applications only, where 256Mbit addressing is supported.
INFINEON Technologies
1
2002-08-06
1 page  
HYS64V64220GBDL-7/7.5/8-D
144 pin SO-DIMM SDRAM Modules
Absolute Maximum Ratings
Parameter
Symbol
Limit Values
min.
max.
Input / Output voltage relative to VSS
VIN, VOUT – 1.0
4.6
Power supply voltage on VDD
VDD – 1.0 4.6
Storage temperature range
TSTG
-55
+125
Power dissipation
PD –
16
Data out current (short circuit)
IOS –
50
Permanent device damage may occur if “Absolute Maximum Ratings” are exceeded.
Functional operation should be restricted to recommended operation conditions.
Exposure to higher than recommended voltage for extended periods of time affect device reliability
Unit
V
V
oC
W
mA
DC Characteristics
TA = 0 to 70 °C; VSS = 0 V; VDD = 3.3 V ± 0.3 V
Parameter
Input high voltage
Input low voltage
Output high voltage (IOUT = – 4.0 mA)
Output low voltage (IOUT = 4.0 mA)
Input leakage current, any input
(0 V < VIN < 3.6 V, all other inputs = 0 V)
Output leakage current
(DQ is disabled, 0 V < VOUT < VDD)
Symbol
VIH
VIL
VOH
VOL
II(L)
IO(L)
Limit Values
min.
max.
2.0 VDD+0.3
– 0.5
0.8
2.4 –
– 0.4
– 20 20
Unit
V
V
V
V
µA
– 20 20 µA
Capacitance
TA = 0 to 70 °C; VDD = 3.3 V ± 0.3 V, f = 1 MHz
Parameter
Symbol
Input capacitance (A0 to A11, BA0, BA1)
Input capacitance (RAS, CAS, WE)
Input Capacitance (CLK0, CLK1)
Input capacitance (CS0, CS1)
Input capacitance (DQMB0-DQMB7)
Input capacitance (CKE0, CKE1)
Input / Output capacitance (DQ0-DQ63)
Input Capacitance (SCL,SA0-2)
Input/Output Capacitance (SDA)
CI1
CI2
CI3
CI4
CI5
CI6
CIO
Csc
Csd
Limit
Values
64M x 64
max.
85
85
70
60
15
50
18
8
10
Unit
pF
pF
pF
pF
pF
pF
pF
pF
pF
Infineon Technologies
5
2002-08-06
5 Page 
HYS64V64220GBDL-7/7.5/8-D
144 pin SO-DIMM SDRAM Modules
Serial Presence Detects
A serial presence detect storage device - E2PROM - is assembled onto the module. Information
about the module configuration, speed, etc. is written into the E2PROM device during module
production using a serial presence detect protocol ( I2C synchronous 2-wire bus)
SPD-Table:
Byte#
Description
0 Number of SPD bytes
1 Total bytes in Serial PD
2 Memory Type
3 Number of Row Addresses
(without BS)
4 Number of Column Addresses
5 Number of DIMM Banks
6 Module Data Width
7 Module Data Width (cont’d)
8 Module Interface Levels
9 SDRAM Cycle Time at CL=3
10 SDRAM Access time from Clock at
CL=3
11 Dimm Config (Error Det/Corr.)
12 Refresh Rate/Type
13 SDRAM width, Primary
14 Error Checking SDRAM data width
15 Minimum clock delay for back-to-
back random column address
16 Burst Length supported
17 Number of SDRAM banks
18 Supported CAS Latencies
19 CS Latencies
20 WE Latencies
21 SDRAM DIMM module attributes
22 SDRAM Device Attributes :General
23 SDRAM Cycle Time at CL = 2
24 SDRAM Access Time from Clock at
CL=2
25 SDRAM Cycle Time at CL = 1
26 SDRAM Access Time from Clock at
CL=1
27 Minimum Row Precharge Time
SPD Entry Value
128
256
SDRAM
12
10
2
64
0
LVTTL
7.5ns / 10.0 ns
5.4ns / 6.0 ns
none
Self-Refresh, 7,6µs
x8
n/a
tccd = 1 CLK
1, 2, 4 & 8
2
2, & 3
CS latency = 0
Write latency = 0
non buffered/non
reg.
VDD tol +/- 10%
7.5ns / 10.0 ns
5.4ns / 6.0 ns
not supported
not supported
20 ns
64Mx64
-7
75
54
75
54
00
00
0F
Hex
64Mx64
-7.5
64Mx64
-8
80
08
04
0D
0A
02
40
00
01
75 A0
54 60
00
82
08
00
01
0F
04
06
01
01
00
0E
A0
60
FF FF
FF FF
14
Infineon Technologies
11
2002-08-06
11 Page | ||
| Páginas | Total 13 Páginas | |
| PDF Descargar | [ Datasheet HYS64V64220GBDL.PDF ] | |
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