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PDF HYS64V16300GU-8-C2 Data sheet ( Hoja de datos )
| Número de pieza | HYS64V16300GU-8-C2 | |
| Descripción | 3.3 V 16M x 64/72-Bit 1 Bank 128MByte SDRAM Module 3.3 V 32M x 64/72-Bit 2 Bank 256MByte SDRAM Module 168-Pin Unbuffered DIMM Modules | |
| Fabricantes | Infineon | |
| Logotipo |  |
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HYS 64/72V16300/32220GU
SDRAM-Modules
3.3 V 16M x 64/72-Bit 1 Bank 128MByte SDRAM Module
3.3 V 32M x 64/72-Bit 2 Bank 256MByte SDRAM Module
168-Pin Unbuffered DIMM Modules
• 168-Pin unbuffered 8-Byte Dual-In-Line
SDRAM Modules for PC main memory
applications
• PC100-222, PC133-333 and PC133-222
versions
• 1 bank 16M × 64, 16M × 72 and 2 bank
32M × 64, 32M × 72 organzation
• Optimized for byte-write non-parity (x64) or
ECC (x72) applications
• JEDEC standard Synchronous DRAMs
(SDRAM)
• Fully PC board layout compatible to INTEL’s
Rev. 1.0 Module Specification
• SDRAM Performance:
-7 /-7.5
PC133
fCK Max. Clock
Frequency
133
tAC Clock Access 5.4
Time
-8 Unit
PC100
100 MHz
6 ns
• Programmed Latencies:
Product Speed
-7 PC133-222
-7.5 PC133-333
-8 PC100-222
CL tRCD
22
33
22
tRP
2
3
2
• Single +3.3 V(±0.3 V) Power Supply
• Programmable CAS Latency, Burst Length,
and Wrap Sequence
(Sequential and Interleave)
• Auto-Refresh (CBR) and Self-Refresh
• Decoupling capacitors mounted on substrate
• All inputs and outputs are LVTTL compatible
• Serial Presence Detect with E2PROM
• Utilizes 16M × 8 SDRAMs in TSOPII-54
packages with 4096 refresh cycles every
64 ms
• 133.35 mm × 31.75 mm × 4,00 mm card size
with gold-contact pads
(JEDEC MO-161-BA)
Description
The HYS 64(72)V16300GU and HYS 64(72)V32220GU are industry-standard 168-pin 8-byte Dual
In-line Memory Modules (DIMMs) which are organized as 16M × 64, 16M × 72 in 1 bank and
32M × 64 and 32M × 72 in two banks of high-speed memory arrays designed with 128Mbit
Synchronous DRAMs (SDRAMs) for non-parity and ECC applications. The DIMMs use -7 speed
sorted 16M × 8 SDRAM devices in TSOP54 packages to meet the PC133-222 requirements, -7.5
speed sorted for PC133-333 and use -8 components for the standard PC100-222 applications.
Decoupling capacitors are mounted on the PC board. The PC board design is in accordance with
INTEL’s Module Specification. The DIMMs have Serial Presence Detect, implemented with a serial
E2PROM using the two-pin I2C protocol. The first 128 bytes are utilized by the DIMM manufacturer
and the second 128 bytes are available to the end user. All INFINEON 168-pin DIMMs provide a
high performance, flexible 8-byte interface in a 133.35 mm long footprint, with 1.25“ (31.75 mm)
height.
INFINEON Technologies
1
9.01
1 page  
HYS 64/72V16300/32220GU
SDRAM-Modules
WE
CS0
DQMB0
DQ(7:0)
CS WE
DQM
DQ0-DQ7
D0
DQMB4
DQ(39:32)
CS WE
DQM
DQ0-DQ7
D4
DQMB1
DQ(15:8)
CS WE
DQM
DQ0-DQ7
D1
DQMB5
DQ(47:40)
CS WE
DQM
DQ0-DQ7
D5
CB(7:0)
CS2
DQMB2
DQ(23:16)
CS WE
DQM
DQ0-DQ7
D8
CS WE
DQM
DQ0-DQ7
D2
DQMB6
DQ(55:48)
CS WE
DQM
DQ0-DQ7
D6
DQMB3
DQ(31:24)
CS WE
DQM
DQ0-DQ7
D3
A0-A11, BA0, BA1
D0-D7, (D8)
VCC
VSS
RAS
D0-D7, (D8)
C0-C15, (C16, C17)
D0-D7, (D8)
D0-D7, (D8)
CAS
D0-D7, (D8)
CKE0
D0-D7, (D8)
Note: D8 is only used in the x72 ECC version and
all resistor values are 10 Ohm except
otherwise noted.
DQMB7
DQ(63:56)
CS WE
DQM
DQ0-DQ7
D7
E2PROM (256 word x 8 Bit)
SA0 SA0
SA1 SA1 SDA
SA2 SA2 WP
SCL SCL
47 k Ω
Clock Wiring
16 M x 64
16 M x 72
CLK0
CLK1
CLK2
CLK3
4 SDRAM+ 3.3 pF
Termination
4 SDRAM+ 3.3 pF
Termination
5 SDRAM
Termination
4 SDRAM+ 3.3 pF
Termination
Block Diagram for 16M x 64/72 SDRAM DIMM Modules (HYS 64/72V16300GU)
INFINEON Technologies
5
9.01
5 Page 
HYS 64/72V16300/32220GU
SDRAM-Modules
Notes
3. All AC characteristics are shown on SDRAM component level.
An initial pause of 100 µs is required after power-up, then a Precharge All Banks command must
be given followed by eight Auto-Refresh (CBR) cycles before the Mode Register Set Operation
can begin.
4. AC timing tests have VIL = 0.4 V and VIH = 2.4 V with the timing referenced to the 1.4 V crossover
point. The transition time is measured between VIH and VIL. All AC measurements assume
tT = 1 ns with the AC output load circuit show. Specified tAC and tOH parameters are measured
with a 50 pF only, without any resistive termination and with a input signal of 1 V/ns edge rate
between 0.8 V and 2.0 V.
5. If clock rising time is longer than 1 ns, a time (tT/2 – 0.5) ns must be added to this parameter.
6. Rated at 1.4 V
7. If tT is longer than 1 ns, a time (tT – 1) ns has to be added to this parameter.
8. Anytime the Refresh Period has been exceeded, a minimum of two Auto-Refresh (CBR)
commands must be given to “wake-up” the device.
9. Timing is asynchronous. If setup time is not met by rising edge of the clock then the CKE signal
is assumed latched on the next cycle.
10.Self-Refresh Exit is a synchronous operation and begins on the second positive clock edge after
CKE returns high. Self-Refresh Exit is not complete until a time period equal to tRC is satisfied
after the Self Refresh Exit command is registered.
11.This is referenced to the time at which the output achieves the open circuit condition, not to
output voltage levels.
CLOCK 1.4 V
tIS t IH
t CH
2.4 V
0.4 V
tCL tT
INPUT
OUTPUT
1.4 V
tAC
t LZ
tAC
t OH
t HZ
1.4 V
IO.vsd
I/O
50 pF
Measurement conditions for
tAC and tOH
A Serial Presence Detect storage device—E2PROM—is assembled onto the module. Information about the
module configuration, speed, etc. is written into the E2PROM device during module production using a Serial
Presence Detect protocol (I2C synchronous 2-wire bus).
INFINEON Technologies
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11 Page | ||
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