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PDF AM29LV081 Data sheet ( Hoja de datos )
| Número de pieza | AM29LV081 | |
| Descripción | 8 Megabit (1 M x 8-Bit) CMOS 3.0 Volt-only Uniform Sector Flash Memory | |
| Fabricantes | AMD | |
| Logotipo |  |
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PRELIMINARY
Am29LV081
8 Megabit (1 M x 8-Bit)
CMOS 3.0 Volt-only Uniform Sector Flash Memory
DISTINCTIVE CHARACTERISTICS
s Optimized architecture for Miniature Card and
mass storage applications
s Single power supply operation
— Full voltage range: 2.7 to 3.6 volt read and write
operations for battery-powered applications
— Regulated voltage range: 3.0 to 3.6 volt read and
write operations and for compatibility with high
performance 3.3 volt microprocessors
s High performance
— Full voltage range: access times as fast as 100
ns
— Regulated voltage range: access times as fast
as 90 ns
s Ultra low power consumption (typical values at
5 MHz)
— 200 nA Automatic Sleep mode current
— 200 nA standby mode current
— 10 mA read current
— 20 mA program/erase current
s Flexible sector architecture
— Sixteen 64 Kbyte sectors
— Supports full chip erase
— Sector Protection features:
A hardware method of locking a sector (using
programming equipment) to prevent any
program or erase operations within that sector
Temporary Sector Unprotect feature allows code
changes in previously locked sectors
s Embedded Algorithms
— Embedded Erase algorithm automatically
preprograms and erases the entire chip or any
combination of designated sectors
— Embedded Program algorithm automatically
writes and verifies data at specified addresses
s Typical 1,000,000 write cycles per sector
(100,000 cycles minimum guaranteed)
s Package option
— 40-pin TSOP
s Compatibility with JEDEC standards
— Pinout and software compatible with single-
power supply Flash
— Superior inadvertent write protection
s Data# Polling and toggle bits
— Provides a software method of detecting
program or erase operation completion
s Ready/Busy# pin (RY/BY#)
— Provides a hardware method of detecting
program or erase cycle completion
s Erase Suspend/Erase Resume
— Suspends an erase operation to read data from,
or program data to, a sector that is not being
erased, then resumes the erase operation
s Hardware reset pin (RESET#)
— Hardware method to reset the device to reading
array data
Publication# 20977 Rev: C Amendment/+1
Issue Date: March 1998
Refer to AMD’s Website (www.amd.com) for the latest information.
1 page  
PRELIMINARY
PIN CONFIGURATION
A0–A19 = 20 addresses
DQ0–DQ7 = 8 data inputs/outputs
CE#
= Chip enable
OE#
= Output enable
WE#
= Write enable
RESET# = Hardware reset pin, active low
RY/BY# = Ready/Busy# output
VCC = 3.0 volt-only single power supply
(see Product Selector Guide for speed
options and voltage supply tolerances)
VSS = Device ground
NC = Pin not connected internally
LOGIC SYMBOL
20
A0–A19
DQ0–DQ7
CE#
OE#
WE#
RESET#
RY/BY#
8
20977C-3
Am29LV081
5
5 Page 
PRELIMINARY
COMMAND DEFINITIONS
Writing specific address and data commands or se-
quences into the command register initiates device op-
erations. Table 4 defines the valid register command
sequences. Writing incorrect address and data val-
ues or writing them in the improper sequence resets
the device to reading array data.
All addresses are latched on the falling edge of WE# or
CE#, whichever happens later. All data is latched on
the rising edge of WE# or CE#, whichever happens
first. Refer to the appropriate timing diagrams in the
“AC Characteristics” section.
Reading Array Data
The device is automatically set to reading array data
after device power-up. No commands are required to
retrieve data. The device is also ready to read array
data after completing an Embedded Program or Em-
bedded Erase algorithm.
After the device accepts an Erase Suspend com-
mand, the device enters the Erase Suspend mode.
The system can read array data using the standard
read timings, except that if it reads at an address
within erase-suspended sectors, the device outputs
status data. After completing a programming opera-
tion in the Erase Suspend mode, the system may
once again read array data with the same exception.
See “Erase Suspend/Erase Resume Commands” for
more information on this mode.
The system must issue the reset command to re-en-
able the device for reading array data if DQ5 goes high,
or while in the autoselect mode. See the “Reset Com-
mand” section, next.
See also “Requirements for Reading Array Data” in the
“Device Bus Operations” section for more information.
The Read Operations table provides the read parame-
ters, and Figure 12 shows the timing diagram.
Reset Command
Writing the reset command to the device resets the de-
vice to reading array data. Address bits are don’t care
for this command.
The reset command may be written between the se-
quence cycles in an erase command sequence before
erasing begins. This resets the device to reading array
data. Once erasure begins, however, the device ig-
nores reset commands until the operation is complete.
The reset command may be written between the se-
quence cycles in a program command sequence be-
fore programming begins. This resets the device to
reading array data (also applies to programming in
Erase Suspend mode). Once programming begins,
however, the device ignores reset commands until the
operation is complete.
The reset command may be written between the se-
quence cycles in an autoselect command sequence.
Once in the autoselect mode, the reset command must
be written to return to reading array data (also applies
to autoselect during Erase Suspend).
If DQ5 goes high during a program or erase operation,
writing the reset command returns the device to read-
ing array data (also applies during Erase Suspend).
See the applicable “AC Characteristics” section for pa-
rameters, and to the Figure 13 for the timing waveforms.
Autoselect Command Sequence
The autoselect command sequence allows the host
system to access the manufacturer and devices codes,
and determine whether or not a sector is protected.
Table 4 shows the address and data requirements. This
method is an alternative to that shown in Table 3, which
is intended for PROM programmers and requires VID
on address bit A9.
The autoselect command sequence is initiated by writ-
ing two unlock cycles, followed by the autoselect com-
mand. The device then enters the autoselect mode,
and the system may read at any address any number
of times, without initiating another command sequence.
A read cycle at address XX00h retrieves the manufac-
turer code. A read cycle at address XX01h returns the
device code. A read cycle containing a sector address
(SA) and the address 02h in it, returns 01h if that sec-
tor is protected, or 00h if it is unprotected. Refer to
Table 2 for valid sector addresses.
The system must write the reset command to exit the
autoselect mode and return to reading array data.
Byte Program Command Sequence
Programming is a four-bus-cycle operation. The pro-
gram command sequence is initiated by writing two un-
lock write cycles, followed by the program set-up
command. The program address and data are written
next, which in turn initiate the Embedded Program al-
gorithm. The system is not required to provide further
controls or timings. The device automatically provides
internally generated program pulses and verify the pro-
grammed cell margin. Table 4 shows the address and
data requirements for the byte program command se-
quence.
When the Embedded Program algorithm is complete,
the device then returns to reading array data and ad-
dresses are no longer latched. The system can deter-
mine the status of the program operation by using DQ7,
DQ6, or RY/BY#. See “Write Operation Status” for in-
formation on these status bits.
Any commands written to the device during the Em-
bedded Program Algorithm are ignored. Note that a
Am29LV081
11
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