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TDA10021HT Schematic ( PDF Datasheet ) - NXP Semiconductors

Teilenummer TDA10021HT
Beschreibung DVB-C channel receiver
Hersteller NXP Semiconductors
Logo NXP Semiconductors Logo 




Gesamt 16 Seiten
TDA10021HT Datasheet, Funktion
INTEGRATED CIRCUITS
DATA SHEET
TDA10021HT
DVB-C channel receiver
Product specification
Supersedes data of 2000 Jun 21
File under Integrated Circuits, IC02
2001 Oct 01






TDA10021HT Datasheet, Funktion
Philips Semiconductors
DVB-C channel receiver
Product specification
TDA10021HT
SYMBOL PIN TYPE(1)
DESCRIPTION
DO[7:4] 37 to 40
O data output bus: this 8-bit parallel data is the output from the TDA10021HT after
demodulation, de-interleaving, RS decoding and de-scrambling. When one of the
two possible parallel interfaces is selected (parameter SERINT = 0, index 20) then
DO[7:0] is the transport stream output. When the serial interface is selected
(parameter SERINT = 1, index 20) then the serial output is on pin DO[0].
VDDDI8
VSSD18
VDDD33
VSSD33
DO[3:0]
41
42
43
44
45 to 48
S digital supply voltage for the core (1.8 V typ.)
G digital ground for the core
S digital supply voltage for the pads (3.3 V typ.)
G digital ground for the pads
O data output bus: this 8-bit parallel data is the output from the TDA10021HT after
demodulation, de-interleaving, RS decoding and de-scrambling. When one of the
two possible parallel interfaces is selected then DO[7:0] is the transport stream
output. When the serial interface is selected then the serial output is on pin DO[0].
VSSD1
VDDD1
VSSA2
VDDA2
Vref(pos)
49
50
51
52
53
G ground return for the digital switching circuitry (ADC)
S power supply input for the digital switching circuitry 1.8 V (ADC)
G ground return for the analog clock drivers (ADC)
S power supply input for the analog clock drivers 3.3 V (ADC)
O this is a positive voltage reference for the ADC. It is derived from the internal band
gap voltage, VBG, with an on-chip fully differential amplifier.
Vref(neg)
54
O this is the negative voltage reference for the ADC. It is derived from the internal
band gap voltage, VBG, with an on-chip fully differential amplifier.
VDDA3
VSSA3
VIM
55 S power supply input for the analog circuits 3.3 V (ADC)
56 G ground return for analog circuits (ADC)
57 I negative input to the ADC: this pin is DC biased to half-supply through an internal
resistor divider (2 × 20 kresistors). In order to stay in the range of the ADC,
VIP VIMshould remain between the input range corresponding to the SW
register (index 1B default value = 0.5 V).
VIP 58 I positive input to the ADC: this pin is DC biased to half-supply through an internal
resistor divider (2 × 20 kresistors). In order to stay in the range of the ADC,
VIP VIMshould remain between the input range corresponding to the SW
register (index 1B default value = 0.5 V).
VSSA3
VDDA3
VCCD(PLL)
DGND
59
60
61
62
G ground return for analog circuits (ADC)
S power supply input for the analog circuits 3.3 V (ADC)
S power supply for the PLL digital section 1.8 V
G ground connection for the PLL digital section
PLLGND
63
G ground connection for the PLL analog section
VCCA(PLL)
64
S power supply for the PLL analog section 3.3 V
Note
1. All inputs (I) are TTL, 5 V tolerant (except pins XIN, VIP and VIM). OD are open-drain outputs, so they must be
connected by a pull-up resistor to either VDDD33 or VDDD50.
2001 Oct 01
6

6 Page









TDA10021HT pdf, datenblatt
Philips Semiconductors
DVB-C channel receiver
PACKAGE OUTLINE
TQFP64: plastic thin quad flat package; 64 leads; body 10 x 10 x 1.0 mm
Product specification
TDA10021HT
SOT357-1
y
48
49
X
33
32 Z E
c
A
64
1
e
pin 1 index
wM
bp
D
HD
17
16
ZD
e
wM
bp
E HE
vM A
A A2 A1
B
vM B
detail X
(A3)
θ
Lp
L
0 2.5 5 mm
scale
DIMENSIONS (mm are the original dimensions)
A
UNIT max. A1 A2 A3 bp
c D(1) E(1) e
HD HE L
Lp
v
w
y
Z D(1)
Z
(1)
E
θ
mm
1.2
0.15
0.05
1.05
0.95
0.25
0.27
0.17
0.18
0.12
10.1
9.9
10.1
9.9
0.5
12.15 12.15
11.85 11.85
1.0
0.75
0.45
0.2
0.08
0.1
1.45 1.45
1.05 1.05
7o
0o
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
OUTLINE
VERSION
SOT357-1
IEC
137E10
REFERENCES
JEDEC
EIAJ
MS-026
EUROPEAN
PROJECTION
ISSUE DATE
99-12-27
00-01-19
2001 Oct 01
12

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