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Número de pieza | TC74VHC573F | |
Descripción | OCTAL D-TYPE LATCH WITH 3-STATE OUTPUT | |
Fabricantes | Toshiba | |
Logotipo | ||
Hay una vista previa y un enlace de descarga de TC74VHC573F (archivo pdf) en la parte inferior de esta página. Total 12 Páginas | ||
No Preview Available ! TC74VHC573F/FW/FT/FK
TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic
TC74VHC573F,TC74VHC573FW,TC74VHC573FT,TC74VHC573FK
Octal D-Type Latch with 3-State Output
The TC74VHC573 is an advanced high speed CMOS OCTAL
LATCH with 3-STATE OUTPUT fabricated with silicon gate
C2MOS technology.
It achieves the high speed operation similar to equivalent
Bipolar Schottky TTL while maintaining the CMOS low power
dissipation.
This 8-bit D-type latch is controlled by a latch enable input
(LE) and a output enable input ( OE ).
When the OE input is high, the eight outputs are in a high
impedance state.
An input protection circuit ensures that 0 to 5.5 V can be
applied to the input pins without regard to the supply voltage.
This device can be used to interface 5 V to 3 V systems and two
supply systems such as battery back up. This circuit prevents
device destruction due to mismatched supply and input voltages.
Features
• High speed: tpd = 4.5 ns (typ.) at VCC = 5 V
• Low power dissipation: ICC = 4 µA (max) at Ta = 25°C
• High noise immunity: VNIH = VNIL = 28% VCC (min)
• Power down protection is provided on all inputs.
• Balanced propagation delays: tpLH ∼− tpHL
• Wide operating voltage range: VCC (opr) = 2 to 5.5 V
• Low noise: VOLP = 1.2 V (max)
• Pin and function compatible with 74ALS573
Note: xxxFW (JEDEC SOP) is not available in
Japan.
TC74VHC573F
TC74VHC573FW
TC74VHC573FT
Weight
SOP20-P-300-1.27A
: 0.22 g (typ.)
SOP20-P-300-1.27
: 0.22 g (typ.)
SOL20-P-300-1.27
: 0.46 g (typ.)
TSSOP20-P-0044-0.65A : 0.08 g (typ.)
VSSOP20-P-0030-0.50 : 0.03 g (typ.)
TC74VHC573FK
1 2006-02-01
1 page TC74VHC573F/FW/FT/FK
AC Characteristics (input: tr = tf = 3 ns)
Characteristics
Propagation delay
time
(LE-Q)
Propagation delay
time
(D-Q)
3-state output enable
time
3-state output disable
time
Output to output skew
Input capacitance
Output capacitance
Power dissipation
capacitance
Symbol
tpLH
tpHL
tpLH
tpHL
tpZL
tpZH
tpLZ
tpHZ
tosLH
tosHL
CIN
COUT
CPD
Test Condition
VCC (V)
3.3 ± 0.3
―
5.0 ± 0.5
3.3 ± 0.3
―
5.0 ± 0.5
RL = 1 kΩ
3.3 ± 0.3
5.0 ± 0.5
RL = 1 kΩ
3.3 ± 0.3
5.0 ± 0.5
3.3 ± 0.3
(Note 1)
5.0 ± 0.5
―
―
CL (pF)
15
50
15
50
15
50
15
50
15
50
15
50
50
50
50
50
Ta = 25°C
Min Typ. Max
― 7.6 11.9
― 10.1 15.4
― 5.0 7.7
― 6.5 9.7
― 7.0 11.0
― 9.5 14.5
― 4.5 6.8
― 6.0 8.8
― 7.3 11.5
― 9.8 15.0
― 5.2 7.7
― 6.7 9.7
― 10.7 14.5
― 6.7 9.7
― ― 1.5
― ― 1.0
― 4 10
―6―
(Note 2) ― 29 ―
Ta =
−40 to 85°C
Min Max
1.0 14.0
1.0 17.5
1.0 9.0
1.0 11.0
1.0 13.0
1.0 16.5
1.0 8.0
1.0 10.0
1.0 13.5
1.0 17.0
1.0 9.0
1.0 11.0
1.0 16.5
1.0 11.0
― 1.5
― 1.0
― 10
――
――
Unit
ns
ns
ns
ns
ns
pF
pF
pF
Note 1: Parameter guaranteed by design.
tosLH = |tpLHm − tpLHn|, tosHL = |tpHLm − tpHLn|
Note 2: CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating
current consumption without load.
Average operating current can be obtained by the equation:
ICC (opr) = CPD·VCC·fIN + ICC/8 (per latch)
And the total CPD when n pcs. of latch operate can be gained by the following equation:
CPD (total) = 21 + 8·n
5 2006-02-01
5 Page Package Dimensions
TC74VHC573F/FW/FT/FK
Weight: 0.03 g (typ.)
11 2006-02-01
11 Page |
Páginas | Total 12 Páginas | |
PDF Descargar | [ Datasheet TC74VHC573F.PDF ] |
Número de pieza | Descripción | Fabricantes |
TC74VHC573F | OCTAL D-TYPE LATCH WITH 3-STATE OUTPUT | Toshiba |
TC74VHC573FK | OCTAL D-TYPE LATCH WITH 3-STATE OUTPUT | Toshiba |
TC74VHC573FT | OCTAL D-TYPE LATCH WITH 3-STATE OUTPUT | Toshiba |
TC74VHC573FW | OCTAL D-TYPE LATCH WITH 3-STATE OUTPUT | Toshiba |
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