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PDF 74LV175 Data sheet ( Hoja de datos )
| Número de pieza | 74LV175 | |
| Descripción | Quad. D-type Flip-Flops with Clear | |
| Fabricantes | Hitachi Semiconductor | |
| Logotipo |  |
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HD74LV175A
Quad. D-type Flip-Flops with Clear
ADE-205-270 (Z)
1st Edition
April 1999
Description
Information at the D inputs of the HD74LV175A is transferred to the Q and Q outputs on the positive going
edge of the clock pulse. Both true and complement outputs from each flip-flop are externally available.
All four flip-flops are controlled by a common clock and common clear. Clearing is accomplished by a
negative pulse at the clear input. All four Q outputs are cleared to a logic low level and all four Q outputs
to a logic high level. Low-voltage and high-speed operation is suitable for battery-powered products (e.g.,
notebook computers), and the low-power consumption extends the battery life.
Features
• VCC = 2.0 V to 5.5 V operation
• All inputs VIH (Max.) = 5.5 V (@VCC = 0 V to 5.5 V)
• All outputs VO (Max.) = 5.5 V (@VCC = 0 V)
• Typical VOL ground bounce < 0.8 V (@VCC = 3.3 V, Ta = 25°C)
• Typical VOH undershoot > 2.3 V (@VCC = 3.3 V, Ta = 25°C)
• Output current ±6 mA (@VCC = 3.0 V to 3.6 V), ±12 mA (@VCC = 4.5 V to 5.5 V)
Function Table
Inputs
CLR
CLK
LX
H↑
H↑
H↓
Note:
H: High level
L: Low level
X: Immaterial
↑: Low to high transition
↓: High to low transition
D
X
H
L
X
Outputs
Q
L
H
L
no change
Q
H
L
H
no change
1 page  
HD74LV175A
DC Electrical Characteristics
• Ta = –40 to 85°C
Item
Symbol
Input voltage
VIH
VIL
Output voltage VOH
VCC (V)*
2.0
2.3 to 2.7
3.0 to 3.6
4.5 to 5.5
2.0
2.3 to 2.7
3.0 to 3.6
4.5 to 5.5
Min to
Max
Min
1.5
VCC × 0.7
VCC × 0.7
VCC × 0.7
—
—
—
—
VCC – 0.1
Typ
—
—
—
—
—
—
—
—
—
Max
—
—
—
—
0.5
VCC × 0.3
VCC × 0.3
VCC × 0.3
—
Unit Test Conditions
V
V IOH = –50 µA
2.3 2.0
—
3.0 2.48 —
4.5 3.8
—
VOL
Min to
—
Max
—
—
—
—
0.1
IOH = –2 mA
IOH = –6 mA
IOH = –12 mA
IOL = 50 µA
Input current
Quiescent
supply current
IIN
ICC
2.3
3.0
4.5
0 to 5.5
5.5
—
—
—
—
—
— 0.4
IOL = 2 mA
— 0.44
IOL = 6 mA
— 0.55
IOL = 12 mA
— ±1
µA VI = 5.5 V or GND
— 20
µA VI = VCC or GND, IO = 0
Output leakage IOFF
0
—
—5
current
µA VI or VO = 0 V to 5.5 V
Input
CIN 3.3 —
capacitance
1.4 —
pF VI = VCC or GND
Note: For conditions shown as Min or Max, use the appropriate values under recommended operating
conditions.
5
5 Page 
• Waveform-1
Timing input
Data input
Input
HD74LV175A
tr
10 %
tsu
90 %
50 % VCC
th
tf
90 %
50 % VCC
10 %
50 % VCC
50 % VCC
tw
50 % VCC
50 % VCC
VCC
0V
VCC
0V
VCC
0V
• Waveform-2
Input
tr
10 %
90 %
50 % VCC
tPLH
tf
90 %
50 % VCC
10 %
tPHL
VCC
0V
In phase output
tPHL
50 % VCC
50 % VCC
tPLH
VOH
VOL
Out of phase output
50 % VCC
50 % VCC
VOH
VOL
Notes: 1. Input waveform: PRR ≤ 1 MHz, Zo = 50 Ω, tr ≤ 3 ns, tf ≤ 3 ns
2. The output is measured one at a time with one transition per measurement.
11
11 Page | ||
| Páginas | Total 15 Páginas | |
| PDF Descargar | [ Datasheet 74LV175.PDF ] | |
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