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PDF 74LCXH16245 Data sheet ( Hoja de datos )
| Número de pieza | 74LCXH16245 | |
| Descripción | Low Voltage 16-Bit Bidirectional Transceiver with Bushold | |
| Fabricantes | Fairchild Semiconductor | |
| Logotipo |  |
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May 2002
Revised May 2002
74LCXH16245
Low Voltage 16-Bit Bidirectional Transceiver
with Bushold
General Description
The LCXH16245 contains sixteen non-inverting bidirec-
tional buffers with 3-STATE outputs and is intended for bus
oriented applications. The device is designed for low volt-
age (2.5V or 3.3V) VCC applications with capability of inter-
facing to a 5V signal environment. The device is byte
controlled. Each byte has separate control inputs which
could be shorted together for full 16-bit operation. The T/R
inputs determine the direction of data flow through the
device. The OE inputs disable both the A and B Ports by
placing them in a high impedance state.
The LCXH16245 data inputs include active bushold cir-
cuitry, eliminating the need for external pull-up resistors to
hold unused or floating data inputs at a valid logic level.
The LCXH16245 is fabricated with an advanced CMOS
technology to achieve high speed operation while maintain-
ing CMOS low power dissipation.
Features
s 2.3V–3.6V VCC specifications provided
s 4.5 ns tPD max (VCC = 3.3V), 20 µA ICC max
s Power-down high impedance outputs
s Bushold on inputs eliminates the need for external
pull-up/pull-down resistors
s ±24 mA output drive (VCC = 3.0V)
s Implements patented noise/EMI reduction circuitry
s Latch-up performance conforms to the requirements of
JESD78
s ESD performance:
Human body model > 2000V
Machine model > 200V
s Also packaged in plastic Fine-Pitch Ball Grid Array
(FBGA)
Ordering Code:
Order Number Package Number
Package Description
74LCXH16245G
(Note 1) (Note 2)
BGA54A
54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide
74LCXH16245MTD
(Note 2)
MTD48
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Note 1: Ordering Code “G” indicates Trays.
Note 2: Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Logic Symbol
© 2002 Fairchild Semiconductor Corporation DS500581
www.fairchildsemi.com
1 page  
AC LOADING and WAVEFORMS Generic for LCX Family
FIGURE 1. AC Test Circuit (CL includes probe and jig capacitance)
Test
tPLH, tPHL
tPZL, tPLZ
tPZH, tPHZ
Switch
Open
6V at VCC = 3.3 ± 0.3V, 2.7V and
VCC x 2 at VCC = 2.5 ± 0.2V
GND
Waveform for Inverting and Non-Inverting Functions
3-STATE Output High Enable and
Disable Times for Logic
Propagation Delay. Pulse Width and trec Waveforms
Setup Time, Hold Time and Recovery Time for Logic
3-STATE Output Low Enable and
Disable Times for Logic
trise and tfall
FIGURE 2. Waveforms
(Input Characteristics; f =1MHz, tr = tf = 3ns)
Symbol
Vmi
Vmo
Vx
Vy
3.3V ± 0.3V
1.5V
1.5V
VOL + 0.3V
VOH − 0.3V
VCC
2.7V
1.5V
1.5V
VOL + 0.3V
VOH − 0.3V
2.5V ± 0.2V
VCC/2
VCC/2
VOL + 0.15V
VOH − 0.15V
5 www.fairchildsemi.com
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| Páginas | Total 8 Páginas | |
| PDF Descargar | [ Datasheet 74LCXH16245.PDF ] | |
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