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74LCX16652MTD Schematic ( PDF Datasheet ) - Fairchild Semiconductor

Teilenummer 74LCX16652MTD
Beschreibung Low Voltage Transceiver/Register with 5V Tolerant Inputs and Outputs
Hersteller Fairchild Semiconductor
Logo Fairchild Semiconductor Logo 




Gesamt 10 Seiten
74LCX16652MTD Datasheet, Funktion
February 1994
Revised April 1999
74LCX16652
Low Voltage Transceiver/Register with 5V Tolerant
Inputs and Outputs
General Description
The LCX16652 contains sixteen non-inverting bidirectional
bus transceivers with 3-STATE outputs providing multi-
plexed transmission of data directly from the input bus or
from the internal registers. Data on the A or B bus will be
clocked into the registers as the appropriate clock pin goes
to the HIGH logic level. Output Enable pins (OEAB, OEBA)
are provided to control the transceiver function (see Func-
tional Description).
The LCX16652 is designed for low-voltage (2.5V or 3.3V)
VCC applications with capability of interfacing to a 5V signal
environment.
The LCX16652 is fabricated with an advanced CMOS tech-
nology to achieve high speed operation while maintaining
CMOS low power dissipation.
Features
s 5V tolerant inputs and outputs
s 2.3V–3.6V VCC specifications provided
s 5.7 ns tPD max (VCC = 3.3V), 20 µA ICC max
s Power down high impedance inputs and outputs
s Supports live insertion/withdrawal (Note 1)
s ±24 mA output drive (VCC = 3.0V)
s Implements patented noise/EMI reduction circuitry
s Latch-up performance exceeds 500 mA
s ESD performance:
Human body model > 2000V
Machine model > 200V
Note 1: To ensure the high-impedance state during power up or down, OE
should be tied to VCC and OE tied to GND through a resistor: the minimum
value or the resistor is determined by the current-sourcing capability of the
driver.
Ordering Code:
Order Number Package Number
Package Description
74LCX16652MEA
MS56A
56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300” Wide
74LCX16652MTD
MTD56
56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Logic Symbol
Pin Descriptions
Pin Names
Description
A0–A15
Data Register A Inputs/3-STATE Outputs
B0–B15
Data Register B Inputs/3-STATE Outputs
CPABn, CPBAn Clock Pulse Inputs
SABn, SBAn
Select Inputs
OEABn, OEBAn Output Enable Inputs
© 1999 Fairchild Semiconductor Corporation DS012005.prf
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74LCX16652MTD Datasheet, Funktion
DC Electrical Characteristics (Continued)
Symbol
Parameter
ICC Quiescent Supply Current
ICC
Increase in ICC per Input
Note 6: Outputs disabled or 3-STATE only.
Conditions
VI = VCC or GND
3.6V VI, VO 5.5V (Note 6)
VIH = VCC 0.6V
VCC
(V)
2.3 3.6
2.3 3.6
2.3 3.6
TA = −40°C to +85°C
Min Max
20
±20
500
Units
µA
µA
AC Electrical Characteristics
TA = −40°C to +85°C, RL = 500
Symbol
Parameter
VCC = 3.3V ± 0.3V
CL = 50 pF
VCC = 2.7V
CL = 50 pF
VCC = 2.5V ± 0.2V
CL = 30 pF
Units
Min Max Min Max Min Max
fMAX
Maximum Clock Frequency
170
MHz
tPHL Propagation Delay
tPLH Bus to Bus
1.5 5.7 1.5 6.2 1.5 6.8
ns
1.5 5.7 1.5 6.2 1.5 6.8
tPHL Propagation Delay
tPLH Clock to Bus
1.5 6.2 1.5 7.0 1.5 7.4
ns
1.5 6.2 1.5 7.0 1.5 7.4
tPHL Propagation Delay
tPLH Select to Bus
1.5 6.5 1.5 7.0 1.5 7.8
ns
1.5 6.5 1.5 7.0 1.5 7.8
tPZL
tPZH
Output Enable Time
1.5 7.0 1.5
1.5 7.0 1.5
8.0 1.5 9.1
8.0 1.5 9.1
ns
tPLZ
tPHZ
Output Disable Time
1.5 6.5 1.5
1.5 6.5 1.5
7.0 1.5 7.8
7.0 1.5 7.8
ns
tS Setup Time
2.5 2.5 3.0 ns
tH Hold Time
1.5 1.5 2.0 ns
tW Pulse Width
3.0 3.0 3.5 ns
tOSHL
tOSLH
Output to Output Skew (Note 7)
1.0
1.0
ns
Note 7: Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The
specification applies to any outputs switching in the same direction, either HIGH-to-LOW (tOSHL) or LOW-to-HIGH (tOSLH). Parameter guaranteed by design.
Dynamic Switching Characteristics
Symbol
Parameter
VOLP
Quiet Output Dynamic Peak VOL
VOLV
Quiet Output Dynamic Valley VOL
Capacitance
Conditions
CL = 50 pF, VIH = 3.3V, VIL = 0V
CL = 30 pF, VIH = 2.5V, VIL =0V
CL = 50 pF, VIH = 3.3V, VIL = 0V
CL = 30 pF, VIH = 2.5V, VIL =0V
VCC
TA = 25°C
Units
(V) Typical
3.3 0.8
2.5 0.6
V
3.3 0.8
2.5 0.6
V
Symbol
CIN
CI/O
CPD
Parameter
Input Capacitance
Input/Output Capacitance
Power Dissipation Capacitance
Conditions
VCC = Open, VI = 0V or VCC
VCC = 3.3V, VI = 0V or VCC
VCC = 3.3V, VI = 0V or VCC, f = 10 MHz
Typical
7
8
20
Units
pF
pF
pF
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