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74LCX00M Schematic ( PDF Datasheet ) - Fairchild Semiconductor

Teilenummer 74LCX00M
Beschreibung Low Voltage Quad 2-Input NAND Gate
Hersteller Fairchild Semiconductor
Logo Fairchild Semiconductor Logo 




Gesamt 13 Seiten
74LCX00M Datasheet, Funktion
December 2013
74LCX00
Low Voltage Quad 2-Input NAND Gate
with 5V Tolerant Inputs
Features
5V tolerant inputs
2.3V–3.6V VCC specifications provided
5.2ns tPD max. (VCC = 3.3V), 10µA ICC max.
Power down high impedance inputs and outputs
±24mA output drive (VCC = 3.0V)
Implements proprietary noise/EMI reduction circuitry
Latch-up performance exceeds JEDEC 78 conditions
ESD performance:
– Human body model > 2000V
– Machine model > 200V
Leadless DQFN package
General Description
The LCX00 contains four 2-input NAND gates. The
inputs tolerate voltages up to 7V allowing the interface of
5V systems to 3V systems.
The 74LCX00 is fabricated with advanced CMOS tech-
nology to achieve high speed operation while maintain-
ing CMOS low power dissipation.
Ordering Information
Package
Order Number Number
Package Description
74LCX00M
M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
74LCX00SJ
74LCX00BQX(1)
M14D
MLP14A
14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
14-Terminal Depopulated Quad Very-Thin Flat Pack No Leads (DQFN), JEDEC
MO-241, 2.5 x 3.0mm
74LCX00MTC
MTC14 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm
Wide
Note:
1. DQFN package available in Tape and Reel only.
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering number.
All packages are lead free per JEDEC: J-STD-020B standard.
©1995 Fairchild Semiconductor Corporation
74LCX00 Rev. 1.7.1
www.fairchildsemi.com






74LCX00M Datasheet, Funktion
AC Loading and Waveforms (Generic for LCX Family)
Test
tPLH, tPHL
tPZL, tPLZ
tPZH, tPHZ
Switch
Open
6V at VCC = 3.3 ± 0.3V
VCC x 2 at VCC = 2.5 ± 0.2V
GND
Figure 1. AC Test Circuit (CL includes probe and jig capacitance)
Waveform for Inverting and Non-Inverting Functions
3-STATE Output High Enable and
Disable Times for Logic
Propagation Delay. Pulse Width and trec Waveforms Setup Time, Hold Time and Recovery Time for Logic
3-STATE Output Low Enable and
Disable Times for Logic
trise and tfall
Symbol
Vmi
Vmo
Vx
Vy
3.3V ± 0.3V
1.5V
1.5V
VOL + 0.3V
VOH – 0.3V
VCC
2.7V
1.5V
1.5V
VOL + 0.3V
VOH – 0.3V
2.5V ± 0.2V
VCC / 2
VCC / 2
VOL + 0.15V
VOH – 0.15V
Figure 2. Waveforms (Input Characteristics; f = 1MHz, tr = tf = 3ns)
©1995 Fairchild Semiconductor Corporation
74LCX00 Rev. 1.7.1
6
www.fairchildsemi.com

6 Page









74LCX00M pdf, datenblatt
Physical Dimensions (Continued)
0.43 TYP
0.65
1.65
0.45
6.10
R0.09 min
12.00°TOP & BOTTOM
A. CONFORMS TO JEDEC REGISTRATION MO-153,
VARIATION AB, REF NOTE 6
B. DIMENSIONS ARE IN MILLIMETERS
1.00
C. DIMENSIONS ARE EXCLUSIVE OF BURRS, MOLD FLASH,
AND TIE BAR EXTRUSIONS
D. DIMENSIONING AND TOLERANCES PER ANSI
Y14.5M, 1982
E. LANDPATTERN STANDARD: SOP65P640X110-14M
F. DRAWING FILE NAME: MTC14REV6
R0.09min
Figure 6. 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or
obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions,
specifically the warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/
©1995 Fairchild Semiconductor Corporation
74LCX00 Rev. 1.7.1
12
www.fairchildsemi.com

12 Page





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