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74HCT193 Schematic ( PDF Datasheet ) - Philips

Teilenummer 74HCT193
Beschreibung Presettable synchronous 4-bit binary up/down counter
Hersteller Philips
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Gesamt 13 Seiten
74HCT193 Datasheet, Funktion
INTEGRATED CIRCUITS
DATA SHEET
For a complete data sheet, please also download:
The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications
The IC06 74HC/HCT/HCU/HCMOS Logic Package Information
The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines
74HC/HCT193
Presettable synchronous 4-bit
binary up/down counter
Product specification
File under Integrated Circuits, IC06
December 1990






74HCT193 Datasheet, Funktion
Philips Semiconductors
Presettable synchronous 4-bit binary
up/down counter
Product specification
74HC/HCT193
(1) Clear overrides load, data and
count inputs.
(2) When counting up the count down
clock input (CPD) must be HIGH,
when counting down the count up
clock input (CPU) must be HIGH.
Sequence
Clear (reset outputs to zero);
load (preset) to binary thirteen;
count up to fourteen, fifteen,
terminal count up, zero, one
and two;
count down to one, zero,
terminal count down, fifteen,
Fig.5 Typical clear, load and count sequence.
December 1990
Fig.6 Logic diagram.
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6 Page









74HCT193 pdf, datenblatt
Philips Semiconductors
Presettable synchronous 4-bit binary
up/down counter
Product specification
74HC/HCT193
(1) HC : VM = 50%; VI = GND to VCC.
HCT: VM = 1.3V; VI = GND to 3 V.
Fig.10 Waveforms showing the master reset input (MR) pulse width, MR to Qn propagation delays, MR to CPU,
CPD removal time and output transition times.
The shaded areas indicate when the input is permitted to
change for predictable output performance.
(1) HC : VM = 50%; VI = GND to VCC.
HCT: VM = 1.3V; VI = GND to 3 V.
Fig.11 Waveforms showing the data input (Dn) to parallel load input (PL) set-up and hold times.
(1) HC : VM = 50%; VI = GND to VCC.
HCT: VM = 1.3V; VI = GND to 3 V.
Fig.12 Waveforms showing the data input (Dn), parallel load input (PL) and the master reset input (MR) to the
terminal count outputs (TCU, TCD) propagation delays.
(1) HC : VM = 50%; VI = GND to VCC.
HCT: VM = 1.3V; VI = GND to 3 V.
Fig.13 Waveforms showing the CPU to CPD or CPD to CPU hold times.
December 1990
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