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MTV212M64I Schematic ( PDF Datasheet ) - ETC

Teilenummer MTV212M64I
Beschreibung 8051 Embedded Monitor Controller Flash Type with ISP
Hersteller ETC
Logo ETC Logo 




Gesamt 26 Seiten
MTV212M64I Datasheet, Funktion
MYSON
TECHNOLOGY
MTV212M64i
(Rev 0.9)
8051 Embedded Monitor Controller
Flash Type with ISP
FEATURES
8051 core, 12MHz operating frequency.
1024-byte RAM; 64K-byte program Flash-ROM support In System Programming(ISP).
Maximum 14 channels of 5V open-drain PWM DAC.
Maximum 32 bi-directional I/O pins.
SYNC processor for composite separation/insertion, H/V polarity/frequency check, polarity adjustment
and programmable clamp pulse output.
Built-in self-test pattern generator with four free-running timings.
Built-in low power reset circuit.
Compliant with VESA DDC1/2B/2Bi/2B+ standard.
Dual slave IIC addresses.
Single master IIC interface for internal device communication.
4-channel 6-bit ADC.
Watchdog timer with programmable intervals.
40-pin DIP, 42-pin SDIP or 44-pin PLCC package.
GENERAL DESCRIPTIONS
The MTV212M64i micro-controller is an 8051 CPU core embedded device especially tailored to Monitor
applications. It includes an 8051 CPU core, 1024-byte SRAM, SYNC processor, 14 built-in PWM DACs,
VESA DDC interface, 4-channel A/D converter and a 64K-byte internal program Flash-ROM.
BLOCK DIAGRAM
P1.0-7
P2.0-2,P2.4-7
P3.2-0
P3.4-5
P0.0-
7
RD
WR
ALE
INT1
RST 8051
X1
X2
P0.0-
7
RD
WR
ALE
INT1
XFR
AD0-2 ADC
H/VSYNC
CONTROL
STOUT
HBLANK
VBLANK
HSYNC
VSYNC
HCLAMP
HALFV
HALFH
14 CHANNEL
PWM DAC
DDC & IIC
INTERFACE
ISCL
ISDA
HSCL
HSDA
This datasheet contains new product information. Myson Technology reserves the rights to modify the product specification without
notice. No liability is assumed as a result of the use of this product. No rights under any patent accompany the sale of the product.
Revision 0.9
-1-
2000/11/16






MTV212M64I Datasheet, Funktion
MYSON
TECHNOLOGY
MTV212M64i
(Rev 0.9)
3. Chip Configuration
The Chip Configuration registers define the chip pins function, as well as the connection, configuration and
frequency of the functional blocks.
Reg name
PADMOD
PADMOD
PADMOD
PADMOD
PADMOD
PADMOD
OPTION
OPTION
XB ANK
addr
30h (w)
31h (w)
32h (w)
3Ah (w)
3Bh (w)
3Ch (w)
33h (w)
34h (w)
35h (r/w)
bit7
DA13E
HIICE
COP17
COP27
PWMF
bit6
DA12E
P56E
IIICE
COP16
COP26
DIV253
bit5
DA11E
P55E
HLFVE
COP15
COP25
FclkE
bit4
DA10E
P54E
HLFHE
COP14
COP24
IICpass
bit3
AD3E
P53E
HCLPE
COP13
COP23
COP56
ENSCL
bit2
AD2E
P52E
P42E
COP12
COP22
COP55
Msel
Xbnk2
bit1 bit0
AD1E AD0E
P51E P50E
P41E P40E
COP11 COP10
COP21 COP20
COP54 COP53
MIICF1 MIICF0
SlvAbs1 SlvAbs0
Xbnk1 Xbnk0
PADMOD (w) : Pad mode control registers. (All are "0" in Chip Reset)
DA13E = 1 Pin “P2.7/DA13” is DA13.
= 0 Pin “P2.7/DA13” is P2.7.
DA12E = 1 Pin “P2.6/DA12” is DA12.
= 0 Pin “P2.6/DA12” is P2.6.
DA11E = 1 Pin “P2.5/DA11” is DA11.
= 0 Pin “P2.5/DA11” is P2.5.
DA10E = 1 Pin “P2.4/DA10” is DA10.
= 0 Pin “P2.4/DA10” is P2.4.
AD3E = 1 Pin “P2.3/AD3” is AD3.
= 0 Pin “P2.3/AD3” is P2.3.
AD2E = 1 Pin “P2.2/AD2” is AD2.
= 0 Pin “P2.2/AD2” is P2.2.
AD1E = 1 Pin “P2.1/AD1” is AD1.
= 0 Pin “P2.1/AD1” is P2.1.
AD0E = 1 Pin “P2.0/AD0” is AD0.
= 0 Pin “P2.0/AD0” is P2.0.
P56E = 1 Pin “DA6/P5.6” is P5.6.
= 0 Pin “DA6/P5.6” is DA6.
P55E = 1 Pin “DA5/P5.5” is P5.5.
= 0 Pin “DA5/P5.5” is DA5.
P54E = 1 Pin “DA4/P5.4” is P5.4.
= 0 Pin “DA4/P5.4” is DA4.
P53E = 1 Pin “DA3/P5.3” is P5.3.
= 0 Pin “DA3/P5.3” is DA3.
P52E = 1 Pin “DA2/P5.2” is P5.2.
= 0 Pin “DA2/P5.2” is DA2.
P51E = 1 Pin “DA1/P5.1” is P5.1.
= 0 Pin “DA1/P5.1” is DA1.
P50E = 1 Pin “DA0/P5.0” is P5.0.
= 0 Pin “DA0/P5.0” is DA0.
HIICE = 1 Pin “HSCL/P3.0/Rxd” is HSCL;
pin “HSDA/P3.1/Txd” is HSDA.
= 0 Pin “HSCL/P3.0/Rxd” is P3.0/Rxd; pin “HSDA/P3.1/Txd” is P3.1/Txd.
IIICE = 1 Pin “ISDA/P3.4/T0” is ISDA;
pin “ISCL/P3.5/T1” is ISCL.
= 0 Pin “ISDA/P3.4/T0” is P3.4/T0;
pin “ISCL/P3.5/T1” is P3.5/T1.
HLFVE = 1 Pin “DA9/HALFV” is VSYNC half frequency output.
Revision 0.9
- 6 - 2000/11/17

6 Page









MTV212M64I pdf, datenblatt
MYSON
TECHNOLOGY
MTV212M64i
(Rev 0.9)
Hor. Total time (A)
Hor. Active time (D)
Hor. F. P. (E)
SYNC pulse width (B)
Hor. B. P. (C)
MTV212M64i Self-Test Pattern Timing
63.5KHz, 60Hz
47.6KHz, 60Hz
31.7KHz, 60Hz
Time H dots Time H dots Time H dots
15.75us 1280 21.0us 1024 31.5us 640
12.05us 979.3 16.07us 783.2 24.05us 488.6
0.2us 16.25 0.28us 12 0.45us
9
1.5us
122
2us
90
3us
61
2us 162.54 2.67us 110
4us 81.27
95.2KHz, 72Hz
Time H dots
10.5us 1600
8.03us 1224
0.14us
21
1.0us
152
1.33us 203
Time
Vert. Total time (O) 16.66ms
Vert. Active time (R) 15.65ms
Vert. F. P. (S)
0.063ms
SYNC pulse width (P) 0.063ms
Vert. B. P. (Q)
0.882ms
V lines
1024
962
3.87
3.87
54.2
Time
16.66ms
15.65ms
0.063ms
0.063ms
0.882ms
V lines
768
721.5
2.9
2.9
40.5
Time
16.66ms
15.65ms
0.063ms
0.063ms
0.882ms
V lines
480
451
1.82
1.82
25.4
Time
13.89ms
13.03ms
0.052ms
0.052ms
0.756ms
V lines
1200
1126
4.5
4.5
65
* 8 x 8 blocks of cross hatch pattern in display region.
6.7 HSYNC Clamp Pulse Output
The HCLAMP output is active by setting “HCLPE” control bit. The leading edge position, pulse width and
polarity of HCLAMP are S/W controllable.
6.8 VSYNC Interrupt
The MTV212M64i checks the VSYNC input pulse and generates an interrupt at its leading edge. The
VSYNC flag is set each time when MTV212M64i detects a VSYNC pulse. The flag is cleared by S/W writing
a "0".
Revision 0.9
- 12 -
2000/11/17

12 Page





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