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ZVNL120G Schematic ( PDF Datasheet ) - Zetex Semiconductors

Teilenummer ZVNL120G
Beschreibung N-CHANNEL ENHANCEMENT MODE LOW THRESHOLD VERTICAL DMOS FET
Hersteller Zetex Semiconductors
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Gesamt 3 Seiten
ZVNL120G Datasheet, Funktion
SOT223 N-CHANNEL ENHANCEMENT MODE
LOW THRESHOLD VERTICAL DMOS FET
ISSUE 2 - JANUARY 1996 7
FEATURES
* VDS - 200V
* RDS(ON) - 10
PARTMARKING DETAIL - ZVNL120
ZVNL120G
D
S
D
G
ABSOLUTE MAXIMUM RATINGS.
PARAMETER
SYMBOL
VALUE
UNIT
Drain-Source Voltage
VDS 200 V
Continuous Drain Current at Tamb=25°C
ID
320 mA
Pulsed Drain Current
IDM 2 A
Gate-Source Voltage
VGS ± 20 V
Power Dissipation at Tamb=25°C
Ptot
2W
Operating and Storage Temperature Range Tj:Tstg
-55 to +150
°C
ELECTRICAL CHARACTERISTICS (at Tamb = 25°C unless otherwise stated).
PARAMETER
SYMBOL MIN. MAX. UNIT CONDITIONS.
Drain-Source Breakdown
Voltage
BVDSS 200
V ID=1mA, VGS=0V
Gate-Source Threshold Voltage VGS(th)
Gate-Body Leakage
IGSS
Zero Gate Voltage Drain
Current
IDSS
0.5
1.5 V
ID=1mA, VDS= VGS
100 nA VGS=± 20V, VDS=0V
10 µA VDS=200V, VGS=0V
100 µA VDS=160V, VGS=0V,
T=125°C(2)
On-State Drain Current(1)
ID(on)
500
Static Drain-Source On-State RDS(on)
Resistance (1)
10
10
Forward Transconductance(1)(2) gfs
Input Capacitance (2)
Ciss
Common Source Output
Capacitance (2)
Coss
200
85
20
mA VDS=25V, VGS=5V
VGS=5V, ID=250mA
VGS=3V, ID=125mA
mS VDS=25V, ID=250mA
pF
pF VDS=25V, VGS=0V, f=1MHz
Reverse Transfer Capacitance (2) Crss
Turn-On Delay Time (2)(3)
td(on)
Rise Time (2)(3)
tr
Turn-Off Delay Time (2)(3)
td(off)
Fall Time (2)(3)
tf
7 pF
8 ns
8 ns VDD25V, ID=250mA
20 ns
12 ns
(1) Measured under pulsed conditions. Width=300µs. Duty cycle 2% (2) Sample test.
(3) Switching times measured with 50source impedance and <5ns rise time on a pulse generator
3 - 420





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