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X17256256DD8B Schematic ( PDF Datasheet ) - Xilinx Inc

Teilenummer X17256256DD8B
Beschreibung QPRO Family of XC1700D QML Configuration PROMs
Hersteller Xilinx Inc
Logo Xilinx  Inc Logo 




Gesamt 10 Seiten
X17256256DD8B Datasheet, Funktion
0
R QPRO Family of XC1700D QML
Configuration PROMs
DS070 (v2.1) June 1, 2000
02
Features
• Certified to MIL-PRF-38535 Appendix A QML
(Qualified Manufacturer Listing.)
• Also available under the following Standard Microcircuit
Drawings (SMD): 5962-94717 and 5962-95617.
• Configuration one-time programmable (OTP) read-only
memory designed to store configuration bitstreams of
Xilinx FPGA devices
• On-chip address counter, incremented by each rising
edge on the clock input
• Simple interface to the FPGA requires only one user
I/O pin
• Cascadable for storing longer or multiple bitstreams
• Programmable reset polarity (active High or active
Low) for compatibility with different FPGA solutions
• Low-power CMOS EPROM process
• Available in 5V version only
• Programming support by leading programmer
manufacturers.
• Design support using the Xilinx Alliance and
Foundation series software packages.
Product Specification
Description
The XC1700D QPRO™ family of configuration PROMs pro-
vide an easy-to-use, cost-effective method for storing Xilinx
FPGA configuration bitstreams.
When the FPGA is in Master Serial mode, it generates a
configuration clock that drives the PROM. A short access
time after the rising clock edge, data appears on the PROM
DATA output pin that is connected to the FPGA DIN pin. The
FPGA generates the appropriate number of clock pulses to
complete the configuration. Once configured, it disables the
PROM. When the FPGA is in Slave Serial mode, the PROM
and the FPGA must both be clocked by an incoming signal.
Multiple devices can be concatenated by using the CEO
output to drive the CE input of the following device. The
clock inputs and the DATA outputs of all PROMs in this
chain are interconnected. All devices are compatible and
can be cascaded with other members of the family.
For device programming, either the Xilinx Alliance™ or the
Foundation™ series development systems compiles the
FPGA design file into a standard HEX format which is then
transferred to most commercial PROM programmers.
VCC VPP GND
RESET/
OE
or
OE/
RESET
CE
CLK
Address Counter
TC
CEO
EPROM
Cell
Matrix
Output
OE
DATA
DS027_01_021500
Figure 1: Simplified Block Diagram (does not show programming circuit)
© 2000 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm.
All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.
DS070 (v2.1) June 1, 2000
Product Specification
www.xilinx.com
1-800-255-7778
1






X17256256DD8B Datasheet, Funktion
QPRO Family of XC1700D QML Configuration PROMs
XC1736D, XC1765D, XC17128D and XC17256D
Absolute Maximum Ratings
R
Symbol
Description
Units
VCC Supply voltage relative to GND
0.5 to +7.0
V
VPP Supply voltage relative to GND
0.5 to +12.5
V
VIN Input voltage relative to GND
0.5 to VCC + 0.5
V
VTS Voltage applied to High-Z output
0.5 to VCC + 0.5
V
TSTG
Storage temperature (ambient)
65 to +150
°C
TSOL
Maximum soldering temperature (10s @ 1/16 in.)
+260
°C
Notes:
1. Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress
ratings only, and functional operation of the device at these or any other conditions beyond those listed under Operating Conditions
is not implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time may affect device reliability.
Operating Conditions
Symbol
VCC
Description
Supply voltage relative to GND (TC = 55°C to +125°C)
Note: During normal read operation VPP must be connected to VCC
DC Characteristics Over Operating Condition
Military
Min
4.50
Max
5.50
Units
V
Symbol
VIH
VIL
VOH
VOL
ICCA
ICCS
IL
CIN
COUT
Description
High-level input voltage
Low-level input voltage
High-level output voltage (IOH = 4 mA) Military
Low-level output voltage (IOL = +4 mA)
Supply current, active mode (at maximum frequency)
Supply current, standby mode
XC17128D, XC17256D
XC1736D, XC1765D
Input or output leakage current
Input capacitance (VIN = GND, f = 1.0 MHz) sample tested
Output capacitance (VIN = GND, f = 1.0 MHz) sample tested
Min Max Units
2.0 VCC V
0 0.8 V
3.7 - V
- 0.4 V
- 10 mA
- 50 µA
- 1.5 mA
10 10 µA
- 10 pF
- 10 pF
6
www.xilinx.com
DS070 (v2.1) June 1, 2000
1-800-255-7778
Product Specification

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