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X1243V8 Schematic ( PDF Datasheet ) - Xicor

Teilenummer X1243V8
Beschreibung Real Time Clock/Calendar/Alarm with EEPROM
Hersteller Xicor
Logo Xicor Logo 




Gesamt 18 Seiten
X1243V8 Datasheet, Funktion
16K
X1243
2-WireRTC
Real Time Clock/Calendar/Alarm with EEPROM
FEATURES
• 2 Alarms—Interrupt Output
—Settable on the Second, 10s of Seconds,
Minute, 10s of Minutes, Hour, Day, Month, or
Day of the Week
—Repeat alarm for time base generation
• 2 Wire Interface interoperable with I2C.
—400kHz data transfer rate
• Secondary Power Supply Input with internal
switch-over circuitry.
• Year 2000 Compliant
• 2K bytes of EEPROM
—64 Byte Page Write Mode
—3 bit Block Lock
• Low Power CMOS
—<1µA Operating Current
—<3mA Active Current during Program
—<400µA Active Current during Data Read
• Single Byte Write Capability
• Typical Nonvolatile Write Cycle Time: 5ms
• High Reliability
—100,000 Endurance Cycles
—Guaranteed Data Retention: 100 Years
• Small Package Options
—8-Lead SOIC Package, 8L TSSOP Package
DESCRIPTION
The X1243 is a Real Time Clock with clock/calendar
circuits and two alarms. The dual port clock and alarm
registers allow the clock to operate, without loss of
accuracy, even during read and write operations.
The clock/calendar provides functionality that is con-
trollable and readable through a set of registers. The
clock, using a low cost 32.768kHz crystal input, accu-
rately tracks the time in seconds, minutes, hours, date,
day, month and years. It has leap year correction,
automatic adjustment for the year 2000 and months
with less than 31 days.
An alarm match of the RTC sets an interrupt flag and
activates an interrupt pin. An alternative alarm function
provides a pulsed interrupt for long time constant time-
bases.
The device offers a backup power input pin. This
Vback pin allows the device to be backed up by a non-
rechargeable battery. The RTC is fully operational
from 1.8 to 5.5 volts.
The X1243 provides a 2K byte EEPROM array, giving
a safe, secure memory for critical user and configura-
tion data. This memory is unaffected by complete fail-
ure of the main and backup supplies.
BLOCK DIAGRAM
32.768kHz
X1
X2
Oscillator
Frequency 1Hz
Divider
Timer
Calendar
Logic
Time
Keeping
Registers
(SRAM)
SCL
SDA
Serial
Interface
Decoder
IRQ
Control
Decode
Logic
8
Control
Registers
(EEPROM)
Status
Register
(SRAM)
Interrupt Enable
Alarm
©Xicor, Inc. 1994, 1995, 1996 Patents Pending
9900-3003.1 4/1/99
1
Alarm
Compare
Alarm Regs
(EEPROM)
16K
EEPROM
Array
Characteristics subject to change without notice






X1243V8 Datasheet, Funktion
X1243
CONTROL REGISTERS
Block Protect Bits - BP2, BP1, BP0 - (Nonvolatile)
The Block Protect Bits, BP2, BP1 and BP0, determine
which blocks of the array are write protected. A write
to a protected block of memory is ignored. The block
protect bits will prevent write operations to one of eight
segments of the array. The partitions are described in
Table 3.
Table 3. Block Protect Bits
Protected Addresses
Array Lock
X1243
000
None
None
001
600h - 7FFh
Upper 1/4
010
400h - 7FFh
Upper 1/2
011
000h - 7FFh
Full Array
100
000h - 03Fh
First Page
101
000h - 07Fh
First 2 pgs
110
000h - 0FFh
First 4 pgs
111
000h - 1FFh
First 8 Pgs
Interrupt Control Bits (AL1E, AL0E)
There are two Interrupt Control bits, Alarm 1 Interrupt
Enable (AL1E) and Alarm 0 Interrupt Enable (AL0E) to
specifically enable or disable the alarm interrupt signal
output. The interrupt output is enabled when either bit is
set to ‘1’. Two volatile bits (AL1 and AL0), associated
with these alarms, indicate if an alarm has happened.
These bits are set on an alarm condition regardless of
whether the alarm interrupts are enabled. The AL1
and AL0 bits are reset by the falling edge of the 8th
clock of a read of the register containing the bits.
In an alternative mode (called pulsed interrupt mode),
controlled by an interrupt mode (IM) bit, the alarm 0
setting provides an output pulse on IRQ each time the
alarm matches the RTC. In this case the AL0 bit is not
used. Alarm 1 works as before (i.e. the AL1 bit is set
when an alarm occurs), but it is necessary to poll the sta-
tus register to determine whether a match has occurred.
This read operation is necessary to reset the AL1 flag.
Normal Mode (IM bit =0)
A match of the RTC and the contents of the alarm 0
registers automatically sets the AL0 bit. If the AL0E bit
is also set, the output IRQ signal goes active (LOW). If
the AL0E bit is not set, the AL0 bit is set, but the IRQ
signal remains unchanged.
A match of the RTC and the contents of the alarm 1
registers automatically sets the AL1 bit. If the AL1E bit
is also set, the output IRQ signal goes active (LOW). If
the AL1E bit is not set, the AL1 bit is set, but the IRQ
signal remains unchanged.
Reading the status register, containing the AL0 and
AL1 bits, resets the bits. The bits do not reset until the
falling edge of the 8th output clock of the status regis-
ter containing the Alarm bits. When the bits reset, the
output IRQ signal returns to the inactive state.
Pulsed Interrupt Mode (IM bit =1)
In this mode, the alarm interrupt enable bits (AL0E and
AL1E) are not used. Alarm 1 operates as before, so a
match of the RTC and Alarm 1 sets the AL1 bit. Since
the interrupt enable bits have no function, it is neces-
sary for the host processor to poll the AL1 bit to deter-
mine if an alarm has occurred.
Alarm 0 provides an output response. In this case,
when the RTC matches the Alarm 0 registers, the out-
put IRQ pulses one time. This pulse can be used to
control some outside circuit or event, without the need
for a local processor. The duration of the pulse is 1024
cycles of the 32.748kHz oscillator. All alarm 0 enable
options are available, so this becomes a very flexible
long term repeat trigger.
WRITING TO THE CLOCK/CONTROL REGISTERS
Changing any of the nonvolatile bits of the clock/con-
trol register requires the following steps:
—Write a 02H to the Status Register to set the Write
Enable Latch (WEL). This is a volatile operation, so
there is no delay after the write. (Operation pre-
ceeded by a start and ended with a stop).
—Write a 06H to the Status Register to set both the
Register Write Enable Latch (RWEL) and the WEL
bit. This is also a volatile cycle. The zeros in the data
byte are required. (Operation preceeded by a start
and ended with a stop).
—Write one to 8 bytes to the Clock/Control Registers
with the desired clock, alarm, or control data. This
sequence starts with a start bit, requires a slave byte
of “11011110” and an address within the CCR and is
terminated by a stop bit. A write to the CCR changes
EEPROM values so these initiate a nonvolatile write
cycle and will take up to 10ms to complete. Writes to
undefined areas have no effect. The RWEL bit is
reset by the completion of a nonvolatile write write
cycle, so the sequence must be repeated to again
6

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X1243V8 pdf, datenblatt
X1243
DEVICE ADDRESSING
Following a start condition, the master must output a
Slave Address Byte. The first four bits of the Slave
Address Byte specify access to the EEPROM array or
to the CCR. Slave bits ‘1010’ access the EEPROM
array. Slave bits ‘1101’ access the CCR.
Bit 3 through Bit 1 of the slave byte specify the device
select bits. These are set to ‘111’.
The last bit of the Slave Address Byte defines the
operation to be performed. When this R/W bit is a one,
then a read operation is selected. A zero selects a
write operation. Refer to Figure 12.
After loading the entire Slave Address Byte from the
SDA bus, the device compares the device identifier
and device select bits with ‘1010111’ or ‘1101111’.
Upon a correct compare, the device outputs an
acknowledge on the SDA line.
Following the Slave Byte is a two byte word address.
The word address is either supplied by the master
device or obtained from an internal counter. On power
up the internal address counter is set to address 0h,
so a current address read of the EEPROM array starts
at address 0. When required, as part of a random
read, the master device must supply the 2 Word
Address Bytes.
In a random read operation, the slave byte in the
“dummy write” portion must match the slave byte in
the “read” section. That is if the random read is from
the array the slave byte must be ‘1010111x’ in both
instances. Similarly, for a random read of the Clock/
Control Registers, the slave byte must be ‘1101111x’
in both places.
Signals from
the Master
SDA Bus
Signals from
the Slave
Slave
AAA
Address C C C
KKK
S
t
o
p
1
A
C Data
K (1)
Data
(2)
Data
(n-1)
Data
(n)
(n is any integer greater than 1)
Figure 12. Sequential Read Sequence
12

12 Page





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