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X1240 Schematic ( PDF Datasheet ) - Xicor

Teilenummer X1240
Beschreibung Real Time Clock/Calendar with EEPROM
Hersteller Xicor
Logo Xicor Logo 




Gesamt 19 Seiten
X1240 Datasheet, Funktion
Preliminary Information
16K
X1240
2-Wire RTC
Real Time Clock/Calendar with EEPROM
FEATURES
• 2-Wire Interface interoperable with I2C.
—400kHz data transfer rate
• Secondary Power Supply Input with internal
switch-over circuitry.
• Year 2000 Compliant
• 2K bytes of EEPROM
—64 Byte Page Write Mode
—3 bit Block Lock
• Low Power CMOS
—<1µA Operating Current
—<3mA Active Current during Program
—<400µA Active Current during Data Read
• Single Byte Write Capability
• Typical Nonvolatile Write Cycle Time: 5ms
• High Reliability
—1,000,000 Endurance Cycles
—Guaranteed Data Retention: 100 Years
• Small Package Options
—8-Lead SOIC Package, 8L TSSOP Package
DESCRIPTION
The X1240 is a Real Time Clock with clock/calendar
circuits. The dual port clock register allows the clock to
operate, without loss of accuracy, even during read and
write operations.
The clock/calendar provides functionality that is con-
trollable and readable through a set of registers. The
clock, using a low cost 32.768kHz crystal input, accu-
rately tracks the time in seconds, minutes, hours, date,
day, month and years. It has leap year correction,
automatic adjustment for the year 2000 and months
with less than 31 days.
The device offers a backup power input pin. This
Vback pin allows the device to be backed up by a non-
rechargeable battery. The RTC is fully operational
from 1.8 to 5.5 volts.
The X1240 provides a 2K byte EEPROM array, giving
a safe, secure memory for critical user and configura-
tion data. This memory is unaffected by complete fail-
ure of the main and backup supplies.
BLOCK DIAGRAM
32.768kHz
X1
X2
Oscillator
Frequency 1Hz
Divider
Timer
Calendar
Logic
Time
Keeping
Registers
(SRAM)
SCL
SDA
Serial
Interface
Decoder
Control
Decode
Logic
8
Control
Registers
(EEPROM)
Status
Register
(SRAM)
16K
EEPROM
Array
©Xicor, Inc. 1994, 1995, 1996, 1997, 1998, 1999 Patents Pending
9900-3003.5 12/6/99 CM
1
Characteristics subject to change without notice






X1240 Datasheet, Funktion
X1240
SERIAL COMMUNICATION
Interface Conventions
The device supports a bidirectional bus oriented proto-
col. The protocol defines any device that sends data
onto the bus as a transmitter, and the receiving device
as the receiver. The device controlling the transfer is
called the master and the device being controlled is
called the slave. The master always initiates data
transfers, and provides the clock for both transmit and
receive operations. Therefore, the devices in this fam-
ily operate as slaves in all applications.
Clock and Data
Data states on the SDA line can change only during
SCL LOW. SDA state changes during SCL HIGH are
reserved for indicating start and stop conditions. See
Figure 3.
Start Condition
All commands are preceded by the start condition,
which is a HIGH to LOW transition of SDA when SCL
is HIGH. The device continuously monitors the SDA
and SCL lines for the start condition and will not
respond to any command until this condition has been
met. See Figure 3.
Stop Condition
All communications must be terminated by a stop con-
dition, which is a LOW to HIGH transition of SDA when
SCL is HIGH. The stop condition is also used to place
the device into the Standby power mode after a read
sequence. A stop condition can only be issued after
the transmitting device has released the bus Refer to
Figure 3.
Figure 3. Valid Data Changes on the SDA Bus
SCL
SDA
Data Stable Data Change Data Stable
Figure 4. Valid Start and Stop Conditions
SCL
SDA
Start
Stop
6

6 Page









X1240 pdf, datenblatt
X1240
Figure 13. Slave Address, Word Address, and Data Bytes (64 Byte pages)
Array
CCR
Device Identifier
1010
1101
00 0 0
11
1 R/W Slave Address Byte
Byte 0
High Order Word Address
0 A10 A9 A8 Byte 1
Low Order Word Address
A7 A6 A5 A4 A3 A2 A1 A0
Byte 2
D7 D6 D5 D4 D3 D2 D1 D0 Data Byte
Byte 3
12

12 Page





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