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PDF WM8150 Data sheet ( Hoja de datos )
| Número de pieza | WM8150 | |
| Descripción | SINGLE CHANNEL 12 BIT CIS/CCD AFE WITH 4 BIT WIDE OUTPUT | |
| Fabricantes | Wolfson Microelectronics plc | |
| Logotipo |  |
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WM8150
Single Channel 12-bit CIS/CCD AFE with 4-bit Wide Output
DESCRIPTION
The WM8150 is a 12-bit analogue front end/digitiser IC
which processes and digitises the analogue output signals
from CCD sensors or Contact Image Sensors (CIS) at pixel
sample rates of up to 8MSPS.
The device includes a complete analogue signal processing
channel containing Reset Level Clamping, Correlated
Double Sampling, Programmable Gain and Offset adjust
functions. Internal multiplexers allow fast switching of offset
and gain for line-by-line colour processing. The output from
this channel is time multiplexed into a high-speed 12-bit
Analogue to Digital Converter. The digital output data is
available in 4-bit wide multiplexed format.
An internal 4-bit DAC is supplied for internal reference level
generation. This may be used during CDS to reference CIS
signals or during Reset Level Clamping to clamp CCD
signals. An external reference level may also be supplied.
ADC references are generated internally, ensuring optimum
performance from the device.
Using an analogue supply voltage of 5V, a digital core
voltage of 5V, and a digital interface supply of either 5V or
3.3V, the WM8150 typically only consumes 160mW when
operating from a single 5V supply.
BLOCK DIAGRAM
FEATURES
• 12-bit ADC
• 8MSPS conversion rate
• Low power - 170mW typical
• 5V single supply or 5V/3.3V dual supply operation
• Single channel operation
• Correlated double sampling
• Programmable gain (8-bit resolution)
• Programmable offset adjust (8-bit resolution)
• Programmable clamp voltage
• 4-bit wide multiplexed data output format
• Internally generated voltage references
• 20-pin SSOP package
• Serial control interface
APPLICATIONS
• Flatbed and sheetfeed scanners
• USB compatible scanners
• Multi-function peripherals
• High-performance CCD sensor interface
VSMP MCLK
AVDD DVDD1 DVDD2
VRT VRX VRB
CL RS VS TIMING CONTROL
VREF/BIAS
VINP
VRLC/VBIAS
RLC
CDS
RLC 4
DAC
WOLFSON MICROELECTRONICS plc
w :: www.wolfsonmicro.com
R M 8 OFFSET
GU
X
DAC
B
RM
GU
X
B
+ PGA
I/P SIGNAL
8 POLARITY
ADJUST
+
W
WM8150
12-
BIT
ADC
DATA
I/O
PORT
OP[0]
OP[1]
OP[2]
OP[3]/SDO
CONFIGURABLE
SERIAL
CONTROL
INTERFACE
SEN
SCK
SDI
AGND1
AGND2
DGND
Production Data, November 2002, Rev 3.0
Copyright 2002 Wolfson Microelectronics plc
1 page  
Production Data
WM8150
Test Conditions
AVDD = DVDD1 = 5.0V, DVDD2 = 3.3V, AGND = DGND = 0V, TA = 25°C, MCLK = 16MHz unless otherwise stated.
PARAMETER
SYMBOL
TEST
CONDITIONS
MIN TYP MAX
Programmable Gain Amplifier
Resolution
Gain equation
8
0.78 + PGA[7 : 0] × 7.57
255
Max gain
Min gain
Gain error
GMAX
GMIN
6.8 8.35 8.7
0.75 0.78 0.82
12
Internal channel offset
Analogue to Digital Converter
VOFF
10
Resolution
12
Maximum Speed
8
Full-scale input range
(2*(VRT-VRB))
VFS
2.5
DIGITAL SPECIFICATIONS
Digital Inputs
High level input voltage
Low level input voltage
High level input current
Low level input current
Input capacitance
Digital Outputs
VIH
VIL
IIH
IIL
CI
0.8 ∗ DVDD2
0.2 ∗ DVDD2
1
1
5
High level output voltage
VOH
IOH = 1mA
DVDD2 - 0.5
Low level output voltage
VOL IOL = 1mA
Supply Currents
0.5
Total supply current − active
35 45
Total analogue AVDD, supply
current − active
IAVDD
30 40
Total digital core, DVDD1,
supply current − active
IDVDD1
1.7 2
Digital I/O supply current,
DVDD2 − active (see note 3)
Supply current − full power down
mode
IDVDD2
45
300 400
Notes:
3. Digital I/O supply current depends on the capacitive load attached to the pin. The Digital I/O supply current is
measured with approximately 50pF attached to the pin.
UNIT
bits
V/V
V/V
V/V
%
mV
bits
MSPS
V
V
V
µA
µA
pF
V
V
mA
mA
mA
mA
µA
w
PD Rev 3.0 November 2002
5
5 Page 
Production Data
WM8150
ADC INPUT BLACK LEVEL ADJUST
The output from the PGA should be offset to match the full-scale range of the ADC (VFS = 2.5V). For
negative-going input video signals, a black level (zero differential) output from the PGA should be
offset to the top of the ADC range by setting register bits PGAFS[1:0]=10. For positive going input
signal the black level should be offset to the bottom of the ADC range by setting PGAFS[1:0]=11.
Bipolar input video is accommodated by setting PGAFS[1:0]=00 or PGAFS[1:0]=01 (zero differential
input voltage gives mid-range ADC output).
OVERALL SIGNAL FLOW SUMMARY
Figure 9 represents the processing of the video signal through the WM8150.
INPUT
SAMPLING OFFSET DAC PGA
ADC BLOCK
BLOCK
BLOCK BLOCK
V VV
x (4095/V )
1
2X
3
+0 if PGAFFSS[1:0]=11
V
+-
++
IN
analog
+4095 if PGAFS[1:0]=10
+2047 if PGAFS[1:0]=0x
CDS = 1
V
RESET
CDS = 0
PGA gain
A = 0.78+(PGA[7:0]*7.57)/255
OUTPUT
INVERT
BLOCK
D
1
digital
D
2
OP[3:0]
D2 = D1 if INVOP = 0
D2 =4095-D1 if INVOP = 1
V
VRLC
VRLCEXT=1
VRLCEXT=0
Offset 260mV*(DAC[7:0]-127.5)/127.5
DAC
RLC
DAC
V *RLCV[3:0] + V
RLCSTEP
RLCBOT
V is VINP voltage sampled on video sample
VIN is VINP sampled during reset clamp
VRESETis voltage applied to VRLC pin
VRLC
CDS, VRLCEXT,RLCV[3:0], DAC[7:0],
PGA[7:0], PGAFS[1:0] and INVOP are set
by programming internal control registers.
CDS=1 for CDS, 0 for non-CDS
Figure 9 Overall Signal Flow
The INPUT SAMPLING BLOCK produces an effective input voltage V1. For CDS, this is the
difference between the input video level VIN and the input reset level VRESET. For non-CDS this is the
difference between the input video level VIN and the voltage on the VRLC/VBIAS pin, VVRLC,
optionally set via the RLC DAC.
The OFFSET DAC BLOCK then adds the amount of fine offset adjustment required to move the
black level of the input signal towards 0V, producing V2.
The PGA BLOCK then amplifies the white level of the input signal to maximise the ADC range,
outputting voltage V3.
The ADC BLOCK then converts the analogue signal, V3, to a 12-bit unsigned digital output, D1.
The digital output is then inverted, if required, through the OUTPUT INVERT BLOCK to produce D2.
CALCULATING OUTPUT FOR ANY GIVEN INPUT
The following equations describe the processing of the video and reset level signals through
the WM8150.
INPUT SAMPLING BLOCK: INPUT SAMPLING AND REFERENCING
If CDS = 1, (i.e. CDS operation) the previously sampled reset level, VRESET, is subtracted from the
input video.
V1 =
VIN - VRESET ................................................................... Eqn. 1
If CDS = 0, (non-CDS operation) the simultaneously sampled voltage on pin VRLC is subtracted
instead.
w
V1 =
VIN - VVRLC .................................................................... Eqn. 2
If VRLCEXT = 1, VVRLC is an externally applied voltage on pin VRLC/VBIAS.
If VRLCEXT = 0, VVRLC is the output from the internal RLC DAC.
PD Rev 3.0 November 2002
11
11 Page | ||
| Páginas | Total 24 Páginas | |
| PDF Descargar | [ Datasheet WM8150.PDF ] | |
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