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W83626D Schematic ( PDF Datasheet ) - Winbond

Teilenummer W83626D
Beschreibung LPC-to-ISA Bridge
Hersteller Winbond
Logo Winbond Logo 




Gesamt 30 Seiten
W83626D Datasheet, Funktion
Winbond W83626F
LPC-to-ISA Bridge






W83626D Datasheet, Funktion
LPC TO ISA BRIDGE SET
W83626F/W83626D
1. PIN DESCRIPTION
I/O12t
I/O24t
I/O12tp3
I/O24tp3
I/OD12t
I/O24t
OUT12
OUT24
O12p3
O24p3
OD12
OD24
INcs
INt
INtd
INtu
INts
INtsp3
- TTL level bi-directional pin with 12 m A source-sink capability
- TTL level bi-directional pin with 24 m A source-sink capability
- 3.3V TTL level bi-directional pin with 12 m A source-sink capability
- 3.3V TTL level bi-directional pin with 24 m A source-sink capability
- TTL level bi-directional pin open drain output with 12 m A sink capability
- TTL level bi-directional pin with 24 m A source-sink capability
- TTL level output pin with 12 m A source-sink capability
- TTL level output pin with 24 m A source-sink capability
- 3.3V TTL level output pin with 12 m A source-sink capability
- 3.3V TTL level output pin with 24 m A source-sink capability
- Open-drain output pin with 12 m A sink capability
- Open-drain output pin with 24 m A sink capability
- CMOS level Schmitt-trigger input pin
- TTL level input pin
- TTL level input pin with internal pull down resistor
- TTL level input pin with internal pull up resistor
- TTL level Schmitt-trigger input pin
- 3.3V TTL level Schmitt-trigger input pin
PRELIMINARY
W83626F PIN DESCRIPTION
LPC Interface
SYMBOL PIN
I/O
FUNCTION
LAD[3:0]
16-19 I/O12tp3 These signal lines communicate address, control and data
information over the LPC bus between a host and a peripheral.
LFRAME#
PCICLK
13 INtsp3 Indicates start of a new cycle or termination of a broken cycle.
PCICLK provides timing for all transactions on the LPC bus. All
21
INt
LPC signals are sampled on the rising edge of PCICLK, and all
timing parameters are defined with respect to this edge.
PCIRST#
14 INtsp3 Reset signal. It can connect to PCIRST# signal on the host.
SERIRQ
LDRQ#
23 I/OD12t Serial IRQ Input/Output.
22 O12tp3 Encoded DMA Request signal.
Publication Release Date: Feb 2000
- 4 - Revision 0.50

6 Page









W83626D pdf, datenblatt
LPC TO ISA BRIDGE SET
W83626F/W83626D
CONFIGURATION REGISTER
1 Chip (Global) Control Register
PRELIMINARY
Enable the following configuration registers by writing 26h to the location 4Eh twice.
Change the location to 2Eh by setting bit4 of CR03 or power-on strapping with a
pulled-down register on pin 128 .
CR03 (ROM Decoder Register, Default , 100011s0b)
Bit 7-5 Reserved.
Bit4 Configure Address and Value
= 0 Write 26h to the location 4E twice. (4Eh and 4Fh are index and data port)
= 1 Write 26h to the location 2E twice(By DACK6 power-on setting with
weak pull-down resistor).(The pair are 2Eh and 2Fh)
Bit 3-2
BIOS Decode Range of High Memory.
= 00 1MB BIOS ROM positive decode.
= 01 2MB BIOS ROM positive decode.
= 10 4MB BIOS ROM positive decode.
= 11 8MB BIOS ROM positive decode. (Default setting)
Bit 1
BIOS ROM decoder Enable.
= 0 Disable BIOS ROM decoder. (Default setting)
=1 Enable BIOS ROM decoder.
Bit 0
BIOS Protected Mode.
=0 BIOS Writed Disable. (Default setting)
=1 BIOS Writed Enable.
This bit set to “ 1 ” for updated BIOS used allow Memory R/W to the range
of BIOS decoded. This bit is always set to “ 0 “ after reset.
- 10 -
Publication Release Date: Feb 2000
Revision 0.50

12 Page





SeitenGesamt 30 Seiten
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