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W83195BR-S Schematic ( PDF Datasheet ) - Winbond

Teilenummer W83195BR-S
Beschreibung STEPLESS 200MHZ 3-DIMM CLOCK FOR SOLANO CHIPSET
Hersteller Winbond
Logo Winbond Logo 




Gesamt 10 Seiten
W83195BR-S Datasheet, Funktion
W83195BR-S
STEPLESS 200MHZ 3-DIMM CLOCK FOR SOLANO CHIPSET
1.0 GENERAL DESCRIPTION
The W83195BR-S is a Clock Synthesizer for Intel 815 Solano chipset. W83195BR-S provides all
clocks required for high-speed RISC or CISC microprocessor and also provides 64 different
frequencies of CPU, SDRAM, PCI, 3V66, IOAPIC clocks frequency setting. All clocks are externally
selectable with smooth transitions.
The W83195BR-S provides I2C serial bus interface to program the registers to enable or disable each
clock outputs and provides 0.25% and 0.5% center type spread spectrum to reduce EMI. A watch
dog timer is quipped and when time out, the RESET# pin will output 4ms pulse signal.
The W83195BR-S provides stepless frequency programming by controlling the VCO freq. and the
clock output divisor ratio. Also the skew of CPU, SDRAM and 3V66 clock outputs are programmable.
The W83195BR-S accepts a 14.318 MHz reference crystal as its input and runs on a 3.3V supply.
High drive PCI and SDRAM CLOCK outputs typically provide greater than 1 V /ns slew rate into 30
pF loads. CPU CLOCK outputs typically provide better than 1 V /ns slew rate into 20 pF loads as
maintaining 50± 5% duty cycle. The fixed frequency outputs as REF, 24MHz, and 48 MHz provide
better than 0.5V /ns slew rate.
2.0 PRODUCT FEATURES
2 CPU clocks
3 3V66 for chipset and AGP clocks
12 SDRAM clocks for 3 DIMMs
8 PCI synchronous clocks.
Optional single or mixed supply:
(VddR = VddP=VddS = Vdd48 = Vdd3 = 3.3V, VddLAPIC=VddLCPU=2.5V)
Skew form CPU to PCI clock -1 to 4 ns, center 2.6 ns
Smooth frequency switch with selections from 66.8 to 200 MHz
I2C 2-Wire serial interface and I2C read back
0.25% and 0.5% center type spread spectrum
Programmable registers to enable/stop each output and select modes
(mode as Tri-state or Normal )
Two 48 MHz pins for USB
24 MHz for super I/O
56-pin SSOP package
Publication Release Date: June 2000
- 1 - Revision 0.42






W83195BR-S Datasheet, Funktion
W83195BR-S
PRELIMINARY
5.1 Register 0: Control Register
Bit @PowerUp
Pin
Description
7X
6X
5X
4X
3X
21
10
01
- FS0#
- FS1#
- FS2#
- FS3#
- FS4#
- If Reg0-bit7=1
0 = ± 0.5% Center type Spread Spectrum Modulation
1 = ± 0.25% Center type Spread Spectrum Modulation
If Reg0-bit7=0
0 = 0 ~ - 1 % Down type Spread Spectrum Modulation
1 = 0 ~ - 0.5% Down type Spread Spectrum Modulation
- 0 = Normal
1 = Spread Spectrum enabled
- 1=CENTER SPREAD 0=DOWN SPREAD
5.2 Register 1 : SDRAM Register (1 = Active, 0 = Inactive)
Bit @PowerUp Pin
Description
7 1 38 SDRAM7 (Active / Inactive)
6 1 41 SDRAM6 (Active / Inactive)
5 1 42 SDRAM5 (Active / Inactive)
4 1 43 SDRAM4 (Active / Inactive)
3 1 44 SDRAM3 (Active / Inactive)
2 1 47 SDRAM2 (Active / Inactive)
1 1 48 SDRAM1 (Active / Inactive)
0 1 49 SDRAM0 (Active / Inactive)
5.3 Register 2: PCI Clock Register (1 = Active, 0 = Inactive)
Bit @PowerUp Pin
Description
7 1 20 PCICLK7 (Active / Inactive)
6 1 19 PCICLK6 (Active / Inactive)
5 1 18 PCICLK5 (Active / Inactive)
4 1 16 PCICLK4 (Active / Inactive)
3 1 15 PCICLK3 (Active / Inactive)
2 1 13 PCICLK2 (Active / Inactive)
1 1 12 PCICLK1 (Active / Inactive)
0 1 11 PCICLK0 (Active / Inactive)
Publication Release Date: June 2000
- 6 - Revision 0.42

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