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W83194R-67B Schematic ( PDF Datasheet ) - Winbond

Teilenummer W83194R-67B
Beschreibung 100MHZ 3-DIMM CLOCK FOR VIA MVP4
Hersteller Winbond
Logo Winbond Logo 




Gesamt 18 Seiten
W83194R-67B Datasheet, Funktion
W83194R-67B
100MHZ 3-DIMM CLOCK FOR VIA MVP4
1.0 GENERAL DESCRIPTION
The W83194R-67B is a Clock Synthesizer which provides all clocks required for high-speed RISC or
CISC microprocessor such as Intel Pentium , AMD and Cyrix. W83194R-67B provides sixteen
CPU/PCI frequencies which are externally selectable with smooth transitions. W83194R-67B also
provides 13 SDRAM clocks controlled by the none-delay buffer_in pin.
The W83194R-67B accepts a 14.318 MHz reference crystal as its input and runs on a 3.3V supply.
Spread spectrum built in at ±0.5% or ±0.25% to reduce EMI. Programmable stopping individual
clock outputs and frequency selection through I2C interface. The device meets the Pentium power-up
stabilization, which requires CPU and PCI clocks be stable within 2 ms after power-up.
High drive six PCI and thirteen SDRAM CLOCK outputs typically provide greater than 1 V /ns slew
rate into 30 pF loads. Two CPU CLOCK outputs typically provide better than 1 V /ns slew rate into 20
pF loads as maintaining 50± 5% duty cycle. The fixed frequency outputs as REF, 24MHz, and 48
MHz provide better than 0.5V /ns slew rate.
2.0 PRODUCT FEATURES
Supports Pentium, AMD, Cyrix CPU with I2C.
4 CPU clocks (one free-running CPU clock)
13 SDRAM clocks for 3 DIMs
6 PCI synchronous clocks
Optional single or mixed supply:
(Vddq1=Vddq2 = Vddq3 = Vddq4 = VddL1 =VddL2= 3.3V) or (Vddq1= Vddq2 = Vddq3=Vddq4 =
3.3V, VddL1 = VdqL2 = 2.5V)
< 250ps skew among CPU and SDRAM clocks
< 4ns propagation delay SDRAM from buffer input
Skew from CPU(earlier) to PCI clock -1 to 4ns, center 2.6ns.
Smooth frequency switch with selections from 60 MHz to 124 MHz CPU
I2C 2-Wire serial interface and I2C read back
0~0.5% down type or ±0.25% or ±0.5% spread spectrum function to reduce EMI
Programmable registers to enable/stop each output and select modes
(mode as Tri-state or Normal )
2ms power up clock stable time
MODE pin for power Management
One 48 MHz for USB & one 24 MHz for super I/O
Packaged in 48-pin SSOP
Publication Release Date: Dec. 1999
- 1 - Revision 0.50






W83194R-67B Datasheet, Funktion
W83194R-67B
PRELIMINARY
8.0 FUNCTION DESCRIPTION
8.1 POWER MANAGEMENT FUNCTIONS
All clocks can be individually enabled or disabled via the 2-wire control interface. On power up,
external circuitry should allow 3 ms for the VCO? to stabilize prior to enabling clock outputs to assure
correct pulse widths. When MODE=0, pins 15 and 46 are inputs (PCI_STOP#), (CPU_STOP#), when
MODE=1, these functions are not available. A particular clock could be enabled as both the 2-wire
serial control interface and one of these pins indicate that it should be enable.
The W83194R-67B may be disabled in the low state according to the following table in order to
reduce power consumption. All clocks are stopped in the low state, but maintain a valid high period
on transitions from running to stop. The CPU and PCI clocks transform between running and stop by
waiting for one positive edge on PCICLK_F followed by negative edge on the clock of interest, after
which high levels of the output are either enabled or disabled.
CPU_STOP# PCI_STOP#
00
01
10
11
CPUCLK 0:2,
SDRAM 0:11
LOW
LOW
RUNNING
RUNNING
PCI
LOW
RUNNING
LOW
RUNNING
SDRAM_F,
CPU_F,PCI_F
RUNNING
RUNNING
RUNNING
RUNNING
OTHER CLKs
RUNNING
RUNNING
RUNNING
RUNNING
8.2 2-W IRE I2C C O N T R O L I N T E R F A C E
The clock generator is a slave I2C component which can be read back? The data stored in the
latches for verification. All proceeding bytes must be sent to change one of the control bytes. The 2-
wire control interface allows each clock output individually enabled or disabled. On power up, the
W83194R-67B initializes with default register settings, and then it is optional to use the 2-wire control
interface.
The SDATA signal only changes when the SDCLK signal is low, and is stable when SDCLK is high
during normal data transfer. There are only two exceptions. One is a high-to-low transition on
SDATA while SDCLK is high used to indicate the beginning of a data transfer cycle. The other is a
low-to-high transition on SDATA while SDCLK is high used to indicate the end of a data transfer
cycle. Data is always sent as complete 8-bit bytes followed by an acknowledge generated.
Byte writing starts with a start condition followed by 7-bit slave address and a write command bit
[1101 0010], command code checking [0000 0000], and byte count checking. After successful
reception of each byte, an acknowledge (low) on the SDATA wire will be generated by the clock chip.
Controller can start to write to internal I2C registers after the string of data. The sequence order is as
follows:
Publication Release Date: Dec.. 1999
- 6 - Revision 0.50

6 Page









W83194R-67B pdf, datenblatt
W83194R-67B
9.3 DC CHARACTERISTICS
PRELIMINARY
Vddq1=Vddq2 = Vddq3 = Vddq4 =3.3V, VddL1 =VddL2= 2.5V , TA = 0°C to +70°C
Parameter
Symbol Min Typ Max Units
Test Conditions
Input Low Voltage
VIL
Input High Voltage
VIH 2.0
Input Low Current
IIL
Input High Current
IIH
Output Low Voltage
VOL
IOL = 4 mA
Output High Voltage
VOH
2.4
IOH = 4mA
Tri-State leakage Current
Ioz
0.8 Vdc
Vdc
-66 µA
5 µA
0.4 Vdc All outputs
Vdc All outputs using 3.3V power
10 µA
Dynamic Supply Current
for Vdd + Vddq3
Idd3
mA CPU = 66.6 MHz
PCI = 33.3 Mhz with load
Dynamic Supply Current
for Vddq2 + Vddq2b
CPU Stop Current
for Vdd + Vddq3
Idd2
ICPUS3
mA Same as above
mA Same as above
CPU Stop Current
for Vddq2 + Vddq2b
ICPUS2
mA Same as above
PCI Stop Current
for Vdd + Vddq3
IPD3
mA
- 12 -
Publication Release Date: Dec.. 1999
Revision 0.50

12 Page





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