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PDF W83194BR-138 Data sheet ( Hoja de datos )
| Número de pieza | W83194BR-138 | |
| Descripción | 200MHZ CLOCK FOR SOLANO CHIPSET | |
| Fabricantes | Winbond | |
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W83194BR-138
200MHZ CLOCK FOR SOLANO CHIPSET
1.0 GENERAL DESCRIPTION
The W83194BR-138 is a Clock Synthesizer for Intel 815 Solano chipset. W83194BR-138 provides all
clocks required for high-speed RISC or CISC microprocessor and also provides 64 different
frequencies of CPU, SDRAM, PCI, 3V66, IOAPIC clocks frequency setting. All clocks are externally
selectable with smooth transitions.
The W83194BR-138 provides I2C serial bus interface to program the registers to enable or disable
each clock outputs and provides 0.25% and 0.5% center type spread spectrum to reduce EMI.
The W83194BR-138 provides stepless frequency programming by controlling the VCO freq. and the
clock output divisor ratio. Also the skew of CPU, SDRAM and 3V66 clock outputs are programmable.
A watch dog timer is quipped and when time out, the RESET# pin will output 4ms pulse signal.
The W83194BR-138 accepts a 14.318 MHz reference crystal as its input and runs on a 3.3V supply.
High drive PCI and SDRAM CLOCK outputs typically provide greater than 1 V /ns slew rate into 30
pF loads. CPU CLOCK outputs typically provide better than 1 V /ns slew rate into 20 pF loads as
maintaining 50± 5% duty cycle. The fixed frequency outputs as REF, 24MHz, and 48 MHz provide
better than 0.5V /ns slew rate.
2.0PRODUCT FEATURES
• 2 CPU clocks
• 3 3V66 clocks
• 9 SDRAM clocks for 2 DIMMs
• 8 PCI synchronous clocks.
• Optional single or mixed supply:
(VDDR = VDDP=VDDS = VDD48 = VDD3 = 3.3V, VDDA=VDDC=2.5V)
• Skew form CPU to PCI clock -1 to 4 ns, center 2.6 ns
• Smooth frequency switch with selections from 66.8 to 200MHz
• I2C 2-Wire serial interface and I2C read back
• 0.25% or 0.5% center type spread spectrum
• Programmable registers to enable/stop each output and select modes
(mode as Tri-state or Normal )
• 48 MHz for USB
• 24 MHz for super I/O
• Packaged in 48-pin SSOP
Publication Release Date: May 2000
- 1 - Revision 0.37
1 page  
W83194BR-138
PRELIMINARY
5.0 FREQUENCY SELECTION BY HARDWARE
FS4 FS3 FS2 FS1 FS0 CPU(MHz)
00000
00001
00010
00011
00100
00101
00110
00111
01000
01001
01010
01011
01100
01101
01110
01111
10000
10001
10010
10011
10100
10101
10110
10111
11000
11001
11010
11011
11100
11101
11110
11111
66.67
66.87
68.67
71.34
100.00
100.30
103.00
107.00
133.33
133.73
137.33
120.00
133.33
133.73
137.33
120.00
136.00
140.00
142.67
145.33
136.00
140.00
142.67
145.33
146.67
153.33
160.00
166.67
146.67
160.00
166.67
200.00
SDRAM
(MHz)
100.00
100.31
103.00
107.00
100.00
100.30
103.00
107.00
133.33
133.73
137.33
120.00
100.00
100.30
103.00
90.00
136.00
140.00
142.67
145.33
102.00
105.00
107.00
109.00
146.67
153.33
160.00
166.67
110.00
120.00
125.00
200.00
3V66(MHz)
66.67
66.87
68.67
71.34
66.67
66.87
68.67
71.33
66.67
66.87
68.67
60.00
66.67
66.87
68.67
60.00
68.00
70.00
71.33
72.67
68.00
70.00
71.34
72.67
73.34
76.67
80.00
83.34
73.34
80.00
83.34
100.00
PCI(MHz)
33.33
33.44
34.33
35.67
33.33
33.43
34.33
35.67
33.33
33.43
34.33
30.00
33.33
33.43
34.33
30.00
34.00
35.00
35.67
36.33
34.00
35.00
35.67
36.33
36.67
38.33
40.00
41.67
36.67
40.00
41.67
50.00
IOAPIC
(MHz)
16.67
16.72
17.17
17.83
16.67
16.72
17.17
17.83
16.67
16.72
17.17
15.00
16.67
16.72
17.17
15.00
17.00
17.50
17.83
18.17
17.00
17.50
17.83
18.17
18.33
19.17
20.00
20.83
18.33
20.00
20.83
25.00
Publication Release Date: May 2000
- 5 - Revision 0.37
5 Page 
W83194BR-138
6.0 SPECIFICATIONS
PRELIMINARY
6.1 ABSOLUTE MAXIMUM RATINGS
Stresses greater than those listed in this table may cause permanent damage to the device.
Precautions should be taken to avoid application of any voltage higher than the maximum rated
voltages to this circuit. Subjection to maximum conditions for extended periods may affect reliability.
Unused inputs must always be tied to an appropriate logic voltage level (Ground or Vdd).
Symbol
Vdd , VIN
TSTG
TB
TA
Parameter
Voltage on any pin with respect to GND
Storage Temperature
Ambient Temperature
Operating Temperature
Rating
- 0.5 V to + 7.0 V
- 65°C to + 150°C
- 55°C to + 125°C
0°C to + 70°C
6.2 AC CHARACTERISTICS
VddR=Vdd3=VddP=VddS=3.3V ± 5 %, VddC = VddA= 2.375V~2.9V , TA = 0°C to +70°C
Parameter
Symbol Min Typ Max Units
Test Conditions
Output Duty Cycle
45 50
55
% Measured at 1.5V
CPU/SDRAM to PCI Offset
tOFF
1
4 ns 15 pF Load Measured at 1.5V
Skew (CPU-CPU), (PCI- tSKEW
PCI), (SDRAM-SDRAM)
250 ps 15 pF Load Measured at 1.5V
CPU/SDRAM
Cycle to Cycle Jitter
tCCJ
±250
ps
CPU/SDRAM
Absolute Jitter
tJA
500 ps
Jitter Spectrum 20 dB
BWJ
500 KHz
Bandwidth from Center
Output Rise (0.4V ~ 2.0V)
& Fall (2.0V ~0.4V) Time
tTLH
tTHL
0.4
1.6 ns 15 pF Load on CPU and PCI
outputs
Overshoot/Undershoot
Beyond Power Rails
Vover
0.7
1.5 V 22 Ω at source of 8 inch PCB
run to 15 pF load
Ring Back Exclusion
VRBE
0.7
2.1 V Ring Back must not enter this
range.
- 11 -
Publication Release Date: May 2000
Revision 0.37
11 Page | ||
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